AD5011 데이터 시트보기 (PDF) - Analog Devices
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AD5011 Datasheet PDF : 8 Pages
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PRELIMINARY TECHNICAL DATA
AD5011
Parameter
AD7346B
Min Typ
Units
Max
Test Conditions/Comments
LOGIC OUTPUTS
Output Logic High, VOH9
Output Logic Low, VOL
POWER SUPPLIES
AVDD, DVDD
IDD
Normal Mode (excluding Driver)
Line Driver
VDD - 0.3
3.15 3.3
32
75
V
0.3 V
3.45 V
mA
mA
IOUT = 200 mA
IOUT = 200 mA
33 W Differential Load
1Operating temperature range is as follows: B Version: –40°C to +85°C.
2The complete transmit path spectrum and pulse shape comply with ETSI requirements. SNR and THD are measured within a 547 kHz bandwidth. Noise and Spurious
tones beyong 540 kHz are therefore excluded.
3The transmit DAC maximum update rate is half the maximum output data rate i.e. 1168 kHz. The maximum transmit clock is 16 x 1168 = 18.688 MHz.
4There are three ranges (bottom range, mid range, top range), each range being divided into eight steps. The transmit filter corner frequency can be set independently from
the receive filter corner frequency. the filter tuning circuit requires a continuous 16.384 MHz clock applied to the Fclk pin.
5Transformer turns ratio = 1:2:3 at 50 kHz when loaded by ETSI (RTR/TM3036) HDSL test loops.
6With 547 kHz filter snd 0 dB PGA gain selected.
7The PGA gain is set by setting the PGA-GC bits in the control register.
8The input switching threshold voltage is approximately 1.2 V to allow interfacing to 2.5 V and 3.3 V logic.
9The output level is determined by the voltage on the logic supply pin VDRIVE.
Specifications subject to change without notice.
REV PrA
–3–
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