AD5011 데이터 시트보기 (PDF) - Analog Devices
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AD5011 Datasheet PDF : 8 Pages
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PRELIMINARY TECHNICAL DATA
AD5011
TIMING CHARACTERISTICS (VDD = +2.7 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted)
Parameter
Limit at
TMIN to TMAX
(B Version)
Units
Test Conditions/Comments
ADCCLK <= 1160kHz
t1
1.5*t3
2*t3
t2
2.5*t3
3*t3
t3
26.939
t4
5
t5
10
1160 kHz < ADCCLK <= 2320 kHz
t6
20
1*t8
t7
1.5*t8
2*t8
t8
26.939
t9
5
t10
10
TRANSMIT DAC
t11
53.5
t12
12
t13
10
t14
t11
t15
3
ns min
ns typ
ns min
ns typ
ns min
ns min
ns min
ns min
ns typ
ns min
ns typ
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t11/2
ADCCLK Rising Edge to SCLK Rising Edge Delay
SCLK Rising Edge to ADCCLK Falling Edge Delay
SCLK Period (1/32*ADCCLK Period)
Data Setup Time Before SCLK Falling Edge
Data Hold Time After SCLK Falling Edge
ADCCLK Rising Edge to SCLK Rising Edge Delay
SCLK Rising Edge to ADCCLK Falling Edge Delay
SCLK Period (1/16*ADCCLK Period)
Data Setup Time Before SCLK Falling Edge
Data Hold Time After SCLK Falling Edge
TxCLK Period (1/18.688 MHz)
Data Setup Time Before TxCLK Rising Edge
Data Hold Time After TxCLK Rising Edge
TxSYNC Low Time
TxCLK Rising Edge to TxSYNC Falling Edge Delay
ns max
CONTROL REGISTER
t16
50
76
t17
15
t16 - 15
t18
15
t16 - 15
t19
t16
t20
7
t21
10
t22
7
t23
10
Guaranteed by design but not production tested.
ns min
ns typ
ns min
ns max
ns min
ns max
ns typ
ns min
ns min
ns min
ns min
SPICLK Period
TFS Setup Time Before SPICLK Falling Edge
TFS Hold Time After SPICLK Falling Edge
TFS High Time
DT Setup Time Before SPICLK Falling Edge
DT Hold Time After SPICLK Falling Edge
DR Setup Time Before SPICLK Falling Edge (R/W = 1)
DR Hold Time After SPICLK Falling Edge (R/W = 1)
t1
t2
ADCCLK
t3
SCLK
t4
t5
SDO
D11 D10
D1 D0
D11 D10 D9
SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges
Figure 1. ADC Timing (ADCCLK <= 1160 kHz)
–4–
REV PrA
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