AD5011B 데이터 시트보기 (PDF) - Analog Devices

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AD5011B

2 Pair/1 Pair ETSI Compatible HDSL Analog Front End

Analog Devices 

PRELIMINARY TECHNICAL DATA

AD5011

t6

t7

ADCCLK

t8

SCLK

SDO

t9

D11 D10

t 10

D1 D0

D11 D10

D1 D0

D11 D10 D9

SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges

Figure 2. ADC Timing (1160 kHz < ADCCLK <= 2320 kHz)

t 15

TxCLK

t 14

t 13

TxSYNC

t 11

TxDATA

t 12

D13 D12 D11

D2 D1 D0 X

X D13 D12

The rising edge of TxSYNC can occur anywhere as long at the TxSYNC low time exceeds one TxCLK period. The TxSYNC falling edge

must occur after the TxCLK rising edge which captures the LSB of the previous word. This ensures correct loading into the DAC. The

first 14 bits are loaded into the DAC, the 2 LSBs being don't cares.

Figure 3. DAC Timing

t 16

SPICLK

t 17

t 18

TFS

t 19

t 21

t 20

DT R/W SEL2 SEL1 SEL0 D11 D10

D1 DO

DR

(R/W = 1)

t 23

t 22

D11 D10

D1 DO

DR

(R/W = 0

If R/W = 1, the selected register's contents will be output on DR. If R/W = 0, no data will be output on DR. The SEL bits identify

which of the four register banks is being written to. The 12 LSBs contain the word. When the AD5011 is reset using RESETB, the

registers are reset to zero.

Figure 4. Control Interface

REV PrA

–5–

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