ARA2008 데이터 시트보기 (PDF) - ANADIGICS

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ARA2008

Reverse Amplifier with Step Attenuator

ANADIGICS 

ARA2008

LOGIC PROGRAMMING

Programming Instructions

The programming word is set through a 6 bit shift

register via the data, clock and enable lines. The

data is entered in order with the most significant bit

(MSB) first and the least significant bit (LSB) last.

The enable line must be low for the duration of the

data entry, then set high to latch the shift register.

The rising edge of the clock pulse shifts each data

value into the register.

Table 7: Programming Word

DATA BIT D5

D4

D3

D2

D1

D0

Value

P5

P4

P3

P2

P1

P0

Table 8: Data Description

VALUE

FUNCTION

(0 = on, 1 = bypass)

P5

32 dB Attenuator Bit

P4

16 dB Attenuator Bit

P3

8 dB Attenuator Bit

P2

4 dB Attenuator Bit

P1

2 dB Attenuator Bit

P0

1 dB Attenuator Bit

DATA

D5: MSB

D4

CLOCK

D3

D2

D1

D0: LSB

ENBL

Figure 4: Serial Data Input Timing

6

ADVANCED PRODUCT INFORMATION - Rev 0.0

10/2001

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