AS1916(2005) 데이터 시트보기 (PDF) - austriamicrosystems AG

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AS1916
(Rev.:2005)

Microprocessor Supervisory Circuits with Manual Reset and Watchdog

austriamicrosystems AG 

AS1916 - AS1918

Data Sheet

austriamicrosystems

RESET/RESETN

8 Detailed Description

The AS1916 - AS1918 supervisory circuits were designed to generate a reset when the monitored supply voltage falls

below its factory-trimmed trip threshold (see VTH on page 3), and to maintain the reset for a minimum timeout period

(see tRP on page 3) after the supply has stabilized.

The integrated watchdog timer (see Watchdog Input on page 8) helps mitigate against bad programming code or clock

signals, and/or poor peripheral response.

The active-low manual reset input (see Manual Reset Input on page 8) allows for an externally activated system reset.

RESET/RESETN

Whenever the monitored supply voltage falls below its reset threshold, the RESET output asserts low or the RESETN

output asserts high. Once the monitored voltage has stabilized, an internal timer keeps the reset asserted for the reset

timeout period (tRP). After the tRP period, the RESET/RESETN output returns to its original state (see Figure 10).

Figure 9. Functional Diagram of VCC Supervisory Application

5

AS1916 - AS1918

VCC

3

MRN

4

WDI

+

–

1.26V

VCC

Reset Timeout

Delay Generator

1

RESETN/

RESET

Watchdog Transition

Detector

Watchdog

Timer

2

GND

Figure 10. Reset Timing Diagram

VCC

1V

RESETN

RESET

GND

VTH

tRP

tRP

VTH

1V

tRD

tRD

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