HT1609 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT1609

2×40 Channel LCD Driver

Holtek Semiconductor 

HT1609L

Functional Description

The HT1609L is an LCD driver LSI with 2×40

segment output channel. It operates with a con-

troller, such as HT163A, or another segment

driver LSI HT1608, HT1608L and HT1609L.

Clock

The CLK1 is the clock to latch data on the

falling edge. It latches the data input from the

bidirectional shift register at the falling edge of

CLK1 and transfers its outputs to the LCD

driver circuit. The CLK2 is the clock to shift

data on the falling edge. It shifts the serial data

at the falling of CLK2 and transfers the output

of each bit of the register to the latch circuit

(refer to Note 1).

Bidirectional shift register

The HT1609L supplies two sets of 40-bit shift

register, which controls the shift direction by

SHF1 & SHF2. The SHF1 controls the 1st 40-

bit shift register, and SHF2 controls the 2nd

40-bit shift register. When SHF1 is connected to

VDD, the 1st shift direction is from Y39 to Y0;

when SHF1 is connected to VSS, the shift direc-

tion changes from Y0 to Y39. When SHF2 is

connected to VDD, the 2nd shift direction is

from Y79 to Y40; when SHF2 is connected to

VSS, the shift direction changes from Y40 to

Y79 (refer to Note 2).

Data input/output

The DL1, DR1, DL2, DR2 are data input or

output option function. When SHF1 (SHF2) is

connected to VDD, the 40th bit data of the 1st

(2nd) 40-bit shift register outputs from DL1

(DL2) ; when SHF1 (SHF2) is connected to VSS

or open , the 1~40 (41~80) bits data from LCD

controller enter into the 1st (2nd) 40-bit shift

through DL1 (DL2).

When SHF1 (SHF2) is connected to VDD, the

1~40 (41~80) bit data from the LCD controller

enter into the 1st (2nd)40-bit shift register

through DR1 (DR2); when SHF1 (SHF2) is con-

nected to VSS or open , the 40th bit shift regis-

ter outputs from DR1 (DR2) (refer to Note 2).

LCD driver circuit

Select one of the four levels of voltage V1, V2,

V3,and V4 for driving an LCD and transfer it to

the output terminals according to the combina-

tion of alternate signal (ALT) and the data in

the latch circuit (refer to Note 1).

8

25th Aug ’98

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