HI7106 데이터 시트보기 (PDF) - Intersil
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HI7106 Datasheet PDF : 11 Pages
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HI7106
V+
1MΩ
HI7106
TO LCD
DECIMAL
POINT
BP 21
TEST
37
TO LCD
BACKPLANE
FIGURE 4. SIMPLE INVERTER FOR FIXED DECIMAL POINT
The second function is a “lamp test”. When TEST is pulled
high (to V+) all segments will be turned on and the display
should read “1888”. The TEST pin will sink about 15mA
under these conditions.
CAUTION: In the lamp test mode, the segments have a constant DC
voltage (no square-wave). This may burn the LCD display if main-
tained for extended periods.
Digital Section
Figures 6 shows the digital section for the HI7106. In the
HI7106, an internal digital ground is generated from a 6V
Zener diode and a large P-Channel source follower.
This supply is made stiff to absorb the relative large capaci-
tive currents when the back plane (BP) voltage is switched.
The BP frequency is the clock frequency divided by 800. For
three readings/sec., this is a 60Hz square wave with a nomi-
nal amplitude of 5V. The segments are driven at the same
frequency and amplitude and are in phase with BP when
OFF, but out of phase when ON. In all cases negligible DC
voltage exists across the segments.
The polarity indication is “on” for negative analog inputs. If
IN LO and IN HI are reversed, this indication can be
reversed also, if desired.
V+
V+
BP
HI7106
DECIMAL
POINT
SELECT
TO LCD
DECIMAL
POINTS
TEST
CD4030
GND
FIGURE 5. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE
a
a
a
a
fb
f bf b
gc
g
g
b
ec
ec ec
d
d
d
BACKPLANE
21
LCD PHASE DRIVER
TYPICAL SEGMENT OUTPUT
V+
0.5mA
2mA
SEGMENT
OUTPUT
INTERNAL DIGITAL GROUND
1000’s
COUNTER
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
CLOCK
†
† THREE INVERTERS
ONE INVERTER SHOWN FOR CLARITY
40
39
7
SEGMENT
DECODE
7
SEGMENT
DECODE
7
SEGMENT
DECODE
LATCH
100’s
10’s
1’s
COUNTER COUNTER COUNTER
÷4
LOGIC CONTROL
INTERNAL
DIGITAL
GROUND
38
VTH = 1V
÷200
1
V+
6.2V
500Ω
TEST
37
26
V-
OSC 1
OSC 2
OSC 3
FIGURE 6. HI7106 DIGITAL SECTION
6
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