74LVQ138MTR(2004) 데이터 시트보기 (PDF) - STMicroelectronics

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74LVQ138MTR
(Rev.:2004)

3 TO 8 LINE DECODER (INVERTING)

STMicroelectronics 

74LVQ138

3 TO 8 LINE DECODER (INVERTING)

s HIGH SPEED:

tPD = 5.5ns (TYP.) at VCC = 3.3 V

s COMPATIBLE WITH TTL OUTPUTS

s LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA=25°C

s LOW NOISE:

VOLP = 0.2V (TYP.) at VCC = 3.3V

s 75Ω TRANSMISSION LINE DRIVING

CAPABILITY

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V

s PCI BUS LEVELS GUARANTEED AT 24 mA

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 138

s IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVQ138 is a low voltage CMOS 3 TO 8

LINE DECODER (INVERTING) fabricated with

sub-micron silicon gate and double-layer metal

wiring C2MOS technology. It is ideal for low power

and low noise 3.3V applications.

SOP

TSSOP

Table 1: Order Codes

PACKAGE

SOP

TSSOP

T&R

74LVQ138MTR

74LVQ138TTR

If the device is enabled, 3 binary select inputs (A,

B, and C) determine which one of the outputs will

go low. If enable input G1 is held low or either G2A

or G2B is held high, the decoding function is

inhibited and all the 8 outputs go to high.

Three enable inputs are provided to ease cascade

connection and application of address decoders

for memory systems.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

Figure 1: Pin Connection And IEC Logic Symbols

July 2004

Rev. 5

1/12

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