AT24C256C(2008) 데이터 시트보기 (PDF) - Atmel Corporation

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AT24C256C
(Rev.:2008)

Two-wire Serial EEPROM 256K (32,768 x 8)

Atmel Corporation 

AT24C256C

1. Pin Descriptions

SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and

negative-edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be

wire-ORed with any number of other open-drain or open-collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired

(directly to GND or to V ) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight

CC

256K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device

Addressing”) A device is selected when a corresponding hardware and software match is true. If these pins are left

floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may

appear during customer applications, Atmel recommends always connecting the address pins to a known state. When

using a pull-up resistor, Atmel recommends using 10kΩ or less.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP

is connected directly to V , all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be

CC

internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications,

Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel

recommends using 10kΩ or less.

3

8568A–SEEPR–11/08

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