AT24C512-10PU-1.8 데이터 시트보기 (PDF) - Atmel Corporation

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AT24C512-10PU-1.8

Two-wire Serial EEPROM 512K (65,536 x 8)

Atmel Corporation 

AT24C512

Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is

open-drain driven and may be wire-ORed with any number of other open-drain or open

collector devices.

DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are

hardwired or left not connected for hardware compatibility with other AT24Cxx devices.

When the pins are hardwired, as many as four 512K devices may be addressed on a

single bus system (device addressing is discussed in detail under the Device Address-

ing section. If the pins are left floating, the A1 and A0 pins will be internally pulled down

to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is

>3 pF, Atmel recommends connecting the address pins to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-

mal write operations. When WP is connected high to VCC, all write operations to the

memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down

to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is

>3 pF, Atmel recommends connecting the pin to GND. Switching WP to VCC prior to a

write operation creates a software write protect function.

Memory Organization AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of

128-bytes each. Random word addressing requires a 16-bit data word address.

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1116O–SEEPR–1/07

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