AT25DF081 데이터 시트보기 (PDF) - Atmel Corporation

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AT25DF081

8-megabit 1.65-volt Minimum SPI Serial Flash Memory

Atmel Corporation 

Figure 2-1. 8-SOIC Top View

CS 1

SO 2

WP 3

GND 4

8 VCC

7 HOLD

6 SCK

5 SI

Figure 2-2. 8-UDFN Top View

CS 1

SO 2

WP 3

GND 4

8 VCC

7 HOLD

6 SCK

5 SI

Figure 2-3. 11-dBGA (Top View

Through Back of Die)

1234

A

NC

B

VCC CS

C

HOLD SO

D

SCK WP

E

SI GND

F

NC

NC

3. Block Diagram

CONTROL AND

CS

PROTECTION LOGIC

SCK

SI

SO

INTERFACE

CONTROL

AND

LOGIC

Y-DECODER

WP

HOLD

X-DECODER

I/O BUFFERS

AND LATCHES

SRAM

DATA BUFFER

Y-GATING

FLASH

MEMORY

ARRAY

4. Memory Array

To provide the greatest flexibility, the memory array of the AT25DF081 can be erased in four lev-

els of granularity including a full chip erase. In addition, the array has been divided into physical

sectors of uniform size, of which each sector can be individually protected from program and

erase operations. The size of the physical sectors is optimized for both code and data storage

applications, allowing both code and data segments to reside in their own isolated

regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the break-

down of each physical sector.

4 AT25DF081

3674E–DFLASH–8/08

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