ATA6602(2009) 데이터 시트보기 (PDF) - Atmel Corporation

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ATA6602
(Rev.:2009)

Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

Atmel Corporation 

3.3 Functional Description

3.3.1

Supply Pin (VS)

The LIN operating voltage is VS = 5V to 18V. After switching on VS, the IC starts with the

Pre-normal mode and the voltage regulator is switched on (that is, 5V/50 mA output capability).

The supply current in Sleep mode is typically 10 µA, and 40 µA in Silent mode.

3.3.2

Ground Pin (GND)

The IC is neutral on the LIN pin in case of GND disconnection; it can handle a ground shift up to

3V for supply voltage at the VS pin above 9V.

3.3.3

Undervoltage Reset Output (NRES)

This push-pull output is supplied from the VCC voltage. If the VCC voltage falls below the under-

voltage detection threshold of Vthun, NRES switches to low after tres_f (Figure 3-8 on page 15)

except the IC is switched into Sleep mode. Even if VCC = 0V the NRES stays low, because it is

internally driven from the VS voltage. If VS voltage ramps down, NRES stays until VS < 1.5V and

then becomes highly resistant.

The implemented undervoltage delay keeps NRES low for tReset = 10 ms after VCC reaches its

normal value.

3.3.4

Voltage Regulator Output Pin (VDD)

The internal 5V voltage regulator is capable of driving loads with up to 50 mA of current con-

sumption; it is able to supply the microcontroller and other ICs on the PCB. It is protected

against overloads by means of current limitation and overtemperature shutdown. Furthermore,

the output voltage is monitored and will cause a reset signal at the NRES output pin if the output

voltage drops below a defined threshold Vthun. To boost up the maximum load current, an exter-

nal NPN transistor may be used with its base connected to the VDD pin and its emitter

connected to PVDD.

3.3.5

Voltage Regulator Sense Pin (PVDD)

This is the sense input pin of the 5V voltage regulator. For normal applications (that is, when

only using the internal output transistor), this pin is connected to the VDD pin. If an external

boosting transistor is used, the PVDD pin must be connected to the output of this transistor, its

emitter terminal.

3.3.6

Bus Pin (LIN)

A low side driver with internal current limitation and thermal shutdown, and an internal pull-up

resistor in compliance with LIN specification 2.0 is implemented. This is a self-adapting current

limitation; that is, during current limitation, as the chip temperature increases, the current

decreases. The allowed voltage range is between –40V and +60V. Reverse currents from the

LIN bus to VS are suppressed, even in case of ground shifts or battery disconnection. LIN

receiver thresholds are compatible to the LIN protocol specification. The fall time from recessive

bus state to dominant, and the rise time from dominant bus state to recessive are slope

controlled.

3.3.7

Input/Output Pin (TXD)

This pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled

to ground in order to have the LIN bus low. If TXD is high, the LIN output transistor is turned off

and the bus is in the recessive state, pulled up by the internal resistor.

6 ATA6602/ATA6603

4921E–AUTO–09/09

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