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ATA6617 데이터 시트보기 (PDF) - Atmel Corporation

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ATA6617 Datasheet PDF : 308 Pages
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Figure 3-9. Timing Sequence with RWD_OSC = 51kΩ
VCC
NRES
Undervoltage Reset
treset = 4ms
NTRIG
td = 155ms
t1
t1 = 20.6ms
t2 = 21ms
twd
Watchdog Reset
tnres = 4ms
t2
3.6.2
ttrig > 200ns
Worst Case Calculation with RWD_OSC = 51 kΩ
The internal oscillator has a tolerance of 20%. This means that t1 and t2 can vary by 20%. The
worst case calculation for the watchdog period twd is calculated below.
The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum
t2.
t1,min = 0.8 × t1 = 16.5ms, t1,max = 1.2 × t1 = 24.8ms
t2,min = 0.8 × t2 = 17.3ms, t2,max = 1.2 × t2 = 26ms
twdmax = t1min + t2min = 16.5ms + 17.3ms = 33.8ms
twdmin = t1max = 24.8ms
twd = 29.3ms ±4.5ms (±15%)
A microcontroller with an oscillator tolerance of ±15% is sufficient to correctly supply the trig-
ger inputs.
Table 3-2. Typical Watchdog Timings
RWD_OSC
kΩ
34
Oscillator
Period
tosc/µs
13.3
Lead
Time
td/ms
105
Closed
Window
t1/ms
14.0
51
19.61
154.8 20.64
91
33.54 264.80 35.32
120
42.84 338.22 45.11
Open Window
t2/ms
14.7
21.67
37.06
47.34
Trigger Period from
Microcontroller
twd/ms
19.9
29.32
50.14
64.05
Reset
Time
tnres/ms
4
4
4
4
18 Atmel ATA6616/ATA6617
9132D–AUTO–12/10

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