ATA6620 데이터 시트보기 (PDF) - Atmel Corporation

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ATA6620

LIN Bus Transceiver with Integrated Voltage Regulator

Atmel Corporation 

ATA6620

4.3 Sleep Mode

A falling edge at EN while TXD is low switches the IC into Sleep mode. The TXD Signal has to

be logic low during the Mode Select window (Figure 4-4 on page 8). We recommend using the

same microcontroller port for EN as for TXD; in this case the mode change is only one

command.

In Sleep mode the transmission path is disabled. Supply current from VBatt is typically

IVSsleep = 10 µA. The VCC regulator is switched off; NRES and RXD are low. The internal slave

termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin

LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and

pin VS is present.

A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period

(Tbus) results in a remote wake-up request. The device switches from Sleep mode to Pre-normal

mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched

on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcon-

troller (Figure 4-5 on page 8).

With EN high you can switch directly from Silent to Normal mode. In the application where the

ATA6620 supplies the microcontroller, the wake-up from Sleep mode is only possible via pin

LIN.

4.4 Pre-normal Mode

At system power-up the device automatically switches to Pre-normal mode. The voltage regula-

tor is switched on (VCC = 5V/50 mA) (see Figure 4-6 on page 9) after typically tVCC > 300 µs. The

NRES output switches to low for tres = 10 ms and sends a reset to the microcontroller. LIN com-

munication is switched off, and the undervoltage detection is active.

A power-down of VBatt (VS < 4.15V) during Silent or Sleep mode switches into Pre-normal mode

after powering up the IC.

4.5 Unpowered Mode

If battery voltage is connected to the application circuit (Figure 4-6 on page 9), the voltage at the

VS pin increases due to the block capacitor. When VS is higher than the VS undervoltage thresh-

old, VSth, the IC-mode changes from Unpowered to Pre-normal mode. The VCC output voltage

reaches nominal value after tVCC. This time depends on the VCC capacitor and the load.

NRES is low for the reset time delay tReset; no mode change is possible during this time.

7

4850D–AUTO–02/06

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