ATC20 데이터 시트보기 (PDF) - Atmel Corporation

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ATC20

Cell-based ASIC

Atmel Corporation 

Features

• Comprehensive Library of Standard Logic and I/O Cells

• ATC20 Core and I/O Cells Designed to Operate with VDD = 1.8V ± 0.15V as Main Target

Operating Conditions

• IO25 and IO33 Pad Libraries Provide Interfaces to 2.5V and 3V Environments

• Oscillators Provide Stable Clock Sources

• Basic Analog Input/Output, Power, Ground and Multiplexer Cells Available,

High-performance Analog Cells Can Be Developed on Request

• Memory Cells Compiled to the Precise Requirements of the Design

• Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard-interface

and Application-specific Cells

Description

The Atmel ATC20 CBIC family is fabricated on a proprietary 0.21 micron five-layer-

metal CMOS process intended for use with a supply voltage of 1.8V ± 0.15V. The fol-

lowing table shows the range for which Atmel library cells have been characterized.

Table 1. Recommended Operating Conditions

Symbol

Parameter

Conditions

VDD

VDD2.5

VDD3.3

VI

VO

TEMP

DC Supply Voltage

DC Supply Voltage

DC Supply Voltage

DC Input Voltage

DC Output Voltage

Operating Free Air

Temperature Range

Core and Standard I/Os

2.5V Interface I/Os

3V Interface I/Os

Industrial

Min Typ Max Unit

1.65 1.8 1.95

V

2.25 2.5 2.75

V

3

3.3 3.6

V

0

VDD

V

0

VDD

V

-40

+85

°C

The Atmel cell libraries and megacell compilers have been designed in order to be

compatible with each other. Simulation representations exist for three types of operat-

ing conditions. They correspond to three characterization conditions defined as

follows:

• MIN conditions:

– TJ = -40°C

– VDD (cell) = 1.95V

– Process = fast (industrial best case)

• TYP conditions:

– TJ = +25°C

– VDD (cell) = 1.8V

– Process = typ (industrial typical case)

• MAX conditions:

– TJ = +100°C

– VDD (cell) = 1.65V

– Process = slow (industrial worst case)

Delays to tri-state are defined as delay to turn off (VGS < VT) of the driving devices.

Output pad drain current corresponds to the output current of the pad when the output

voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to

access resistors (in and out of the die) are taken into account. In order to have accu-

rate timing estimates, all characterization has been run on electrical netlists extracted

from the layout database.

Cell-based ASIC

ATC20

Summary

Rev. 1361BS–CBIC–09/02

1

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