ATC20 데이터 시트보기 (PDF) - Atmel Corporation
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ATC20 Datasheet PDF : 11 Pages
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Atmel Compiled
Megacell Library
The Atmel Compiled Megacell Library enables compilation of megacells for the func-
tions Synchronous RAM, Asynchronous RAM, Asynchronous Dual-port RAM and
Synchronous ROM, according to the user’s precise requirements.
The Atmel megacells can be instanced as often as required in designs and can be used
in parallel with cells from all other Atmel CBIC libraries. All the megacell representations
required for schematic entry, simulation, place and route, layout generation, and verifi-
cation are created automatically.
Compiled Synchronous
RAM Megacells
The Atmel Synchronous RAM compiler has bidirectional or separate I/O ports, and can
be configured in multi-bank form, with a maximum of four banks.
The range of permitted Synchronous RAM megacell configurations is as follows:
Number of bits 128, .. 144K bits
Number of words 32, .. 8K
Word Size
4, .. 36 bits
The following table shows the range of performances for particular Synchronous RAM
configurations under typical conditions.
Configuration
Density (Kbits/mm2)
Frequency (MHz)
Dynamic Power
(mW/MHz)
1K x 8 (8K bits)
51
237
0.17
2K x 16 (32K bits)
58
157
0.36
4K x 32 (128K bits)
62
112
0.73
Compiled Asynchronous
RAM Megacells
The Atmel Asynchronous RAM compiler has bidirectional or separate I/O ports, and can
be configured in multi-bank form, with a maximum of four banks.
The range of permitted Asynchronous RAM megacell configurations is as follows:
Number of bits 128, .. 128K bits
Number of words 16, .. 4K
Word Size
8, .. 36 bits
The following table shows the range of performances for particular Asynchronous RAM
configurations under typical conditions.
Configuration
Density (Kbits/mm2)
Frequency (MHz)
Dynamic Power
(mW/MHz)
1K x 8 (8K bits)
40
270
0.24
2K x 16 (32K bits)
40
268
0.38
4K x 32 (128K bits)
50
185
0.63
8 ATC20 Summary
1361BS–CBIC–09/02
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