ATC13 데이터 시트보기 (PDF) - Atmel Corporation

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ATC13

Cell-based ASIC

Atmel Corporation 

Delays to tristate are defined as delay to turn off (VGS < VT) of the driving devices.

Output pad drain current corresponds to the output current of the pad when the output

voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to access

resistors (in and out of the die) are taken into account. In order to have accurate timing

estimates, all characterization has been run on electrical netlists extracted from the lay-

out database.

2. Standard Cell Library, SClib

The Atmel Standard Cell Library, SClib, contains a comprehensive set of combinational

logic and storage cells. The SClib library includes cells which belong to the following

categories:

• Buffers and Gates

• Multiplexers

• Flip-flops

• Scan Flip-flops

• Latches

• Adders and Subtractors

2.1 Decoding the Cell Name

Table 2-1 shows the naming conventions for the cells in the SClib library. Each cell

name begins with either a two-, three-, or four-letter code that defines the type of cell.

This indicates the range of standard cells available.

Table 2-1. Cell Codes

Code Description

AD Adder

AH Half Adder

AS Adder/Subtractor

AN AND Gate

AOI AND-OR-Invert Gate

AON AND-OR-AND-Invert Gates

AOR AND-OR Gate

BH Bus Holder

BUFB Balanced Buffer

BUFF Non-Inverting Buffer

BUFT Non-Inverting 3-State Buffer

CG Carry Generator

CLK2 Clock Buffer

DE D-Enabled Flip-Flop

DF D Flip-Flop

INV0 Inverter

Code

INVB

INVT

LA

MI

MX

ND

NR

OAI

OAN

OR

ORA

SD

SE

SU

XN

XR

Description

Balanced Inverter

Inverting 3-State Buffer

D Latch

Inverting Multiplexer

Multiplexer

NAND Gate

NOR Gate

OR-AND-Invert Gate

OR-AND-OR-Invert Gates

OR Gate

OR-AND Gate

Multiplexed Scan D Flip-Flop

Multiplexed Scan Enable D Flip-Flop

Subtractor

Exclusive NOR Gate

Exclusive OR Gate

2 ATC13 Summary

6134AS–CASIC–08-Mar-05

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