ATC13 데이터 시트보기 (PDF) - Atmel Corporation

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ATC13

Cell-based ASIC

Atmel Corporation 

ATC13 Summary

7.2 Dual-port Synchronous RAM

Key features of the dual-port synchronous RAM are:

• 300 MHz worst-case cycle time for 4 Kwords x 32 bits

• Zero quiescent current

• 3-state outputs

• Several aspect ratios for optimization of performance

• Separate data-in, data-out pins support a write-through feature

• Asynchronous write-through for testing interface shadow logic

• BIST interface

• Optional sub-word write capability

The dual-port synchronous RAM compiler is a high-density high-speed RAM compiler

with quiescent current consumption equal to zero when the RAM is not in a read or write

mode. The compiler is optimized for a power supply voltage range of 1.1V to 1.32V and

can operate at voltages as low as 0.9V. The DPRAM instances can be built with several

aspect ratios for maximum area and performance optimization. Separate output (Q) and

input (D) pins allow a write-through cycle feature. An asynchronous write-through mode

(AWT) allows testing of interface shadow logic through scan. Built-in self-test (BIST)

interface allows for easy connection to most memBIST solutions. The special test

modes allow externally bypassing read and write self-timed circuits and adjusting read

and write margins. The DPRAM compiler also includes a bit-write feature where selec-

tive write to each I/O can be done. A maskable write enable signal is provided for each

I/O for maximum flexibility.

Table 7-2 gives the range of permitted dual-port synchronous RAM configurations.

Table 7-2. Configuration Range

Parameter

Min

Address Locations (words)

32

Word Size (Number of I/O bits)

2

Total Bits in Core (Word Size x Address Locations)

64

Max

16K

256

512K

Increment

4 x CM(1)

1 bit

Note: 1. CM = 4, 8, 16: Column Mux option

7.3 Via Programmable Ultra-low-power ROM

Key features of the via programmable ROM are:

• 1-port high-density low-power synchronous via-2 programmable ROM

• 76 MHz worst-case cycle time for 8K words x 8 bits

• Zero quiescent current

• 3-state outputs

• Several aspect ratios for optimization of performance

• Programming support

The via programmable ROM compiler is a high-density low-power synchronous ROM

compiler. The quiescent current consumption is zero when the ROM is not enabled. The

compiler is optimized for a power supply voltage range of 1.1V to 1.32V. The ROM

instances can be built with several aspect ratios for maximum area and performance

9

6134AS–CASIC–08-Mar-05

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