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ATF-54143

Low Noise Enhancement Mode Pseudomorphic HEMT in a Surface Mount Plastic Package

HP => Agilent Technologies 

ATF-54143 Applications

Information

Introduction

Agilent Technologies’s ATF-54143

is a low noise enhancement mode

PHEMT designed for use in low

cost commercial applications in

the VHF through 6 GHz frequency

range. As opposed to a typical

depletion mode PHEMT where the

gate must be made negative with

respect to the source for proper

operation, an enhancement mode

PHEMT requires that the gate be

made more positive than the

source for normal operation.

Therefore a negative power

supply voltage is not required for

an enhancement mode device.

Biasing an enhancement mode

PHEMT is much like biasing the

typical bipolar junction transistor.

Instead of a 0.7 V base to emitter

voltage, the ATF-54143 enhance-

ment mode PHEMT requires

about a 0.6V potential between

the gate and source for a nominal

drain current of 60 mA.

Matching Networks

The techniques for impedance

matching an enhancement mode

device are very similar to those

for matching a depletion mode

device. The only difference is in

the method of supplying gate

bias. S and Noise Parameters for

various bias conditions are listed

in this data sheet. The circuit

shown in Figure 1 shows a typical

LNA circuit normally used for

900 and 1900 MHz applications

(Consult the Agilent Technologies

website for application notes

covering specific applications).

High pass impedance matching

networks consisting of L1/C1 and

L4/C4 provide the appropriate

match for noise figure, gain, S11

and S22. The high pass structure

also provides low frequency gain

reduction which can be beneficial

from the standpoint of improving

out-of-band rejection at lower

frequencies.

INPUT

C1

Q1

Zo

L1

L2

C2

R4

R5 C3

R1

R2

C4

OUTPUT

Zo

L4

L3

C5

R3

C6

Vdd

Figure 1. Typical ATF-54143 LNA with Passive

Biasing.

Capacitors C2 and C5 provide a

low impedance in-band RF

bypass for the matching net-

works. Resistors R3 and R4

provide a very important low

frequency termination for the

device. The resistive termination

improves low frequency stability.

Capacitors C3 and C6 provide

the low frequency RF bypass for

resistors R3 and R4. Their value

should be chosen carefully as C3

and C6 also provide a termina-

tion for low frequency mixing

products. These mixing products

are as a result of two or more in-

band signals mixing and produc-

ing third order in-band distortion

products. The low frequency or

difference mixing products are

bypassed by C3 and C6. For best

suppression of third order

distortion products based on the

CDMA 1.25 MHz signal spacing,

C3 and C6 should be 0.1 µF in

value. Smaller values of capaci-

tance will not suppress the

generation of the 1.25 MHz

difference signal and as a result

will show up as poorer two tone

IP3 results.

Whereas a depletion mode

PHEMT pulls maximum drain

current when Vgs = 0V, an en-

hancement mode PHEMT pulls

only a small amount of leakage

current when Vgs= 0V. Only when

Vgs is increased above Vto, the

device threshold voltage, will

drain current start to flow. At a

Vds of 3V and a nominal Vgs of

0.6V, the drain current Id will be

approximately 60 mA. The data

sheet suggests a minimum and

maximum Vgs over which the

desired amount of drain current

will be achieved. It is also impor-

tant to note that if the gate

terminal is left open circuited,

the device will pull some amount

of drain current due to leakage

current creating a voltage differ-

ential between the gate and

source terminals.

Passive Biasing

Passive biasing of the ATF-54143

is accomplished by the use of a

voltage divider consisting of R1

and R2. The voltage for the

divider is derived from the drain

voltage which provides a form of

voltage feedback through the use

of R3 to help keep drain current

constant. Resistor R5 (approxi-

mately 10kΩ) provides current

limiting for the gate of enhance-

ment mode devices such as the

ATF-54143. This is especially

important when the device is

driven to P1dB or PSAT.

Resistor R3 is calculated based

on desired Vds, Ids and available

power supply voltage.

Bias Networks

One of the major advantages of

the enhancement mode technol-

ogy is that it allows the designer

to be able to dc ground the

source leads and then merely

apply a positive voltage on the

gate to set the desired amount of

quiescent drain current Id.

R3 = VDD – Vds (1)

Ids + IBB p

VDD is the power supply voltage.

Vds is the device drain to source

voltage.

Ids is the desired drain current.

I is the current flowing through

BB

the R1/R2 resistor voltage

divider network.

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