ATMEGA323 데이터 시트보기 (PDF) - Atmel Corporation
부품명
상세내역
제조사
ATMEGA323 Datasheet PDF : 247 Pages
| |||
Architectural
Overview
The fast-access Register File concept contains 32 x 8-bit general purpose working reg-
isters with a single clock cycle access time. This means that during one single clock
cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output
from the Register File, the operation is executed, and the result is stored back in the
Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for look up tables in Flash Program
memory. These added function registers are the 16-bits X-, Y-, and Z-register.
The ALU supports arithmetic and logic operations between registers or between a con-
stant and a register. Single register operations are also executed in the ALU. Figure 5
shows the ATmega323 AVR Enhanced RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be
used on the Register File as well. This is enabled by the fact that the Register File is
assigned the 32 lowest Data Space addresses ($00 - $1F), allowing them to be
accessed as though they were ordinary memory locations.
The I/O Memory space contains 64 addresses for CPU peripheral functions as Control
Registers, Timer/Counters, A/D Converters, and other I/O functions. The I/O Memory
can be accessed directly, or as the Data Space locations following those of the Register
File, $20 - $5F.
8 ATmega323(L)
1457G–AVR–09/03
Share Link: 