ATMEGA323 데이터 시트보기 (PDF) - Atmel Corporation
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ATMEGA323 Datasheet PDF : 247 Pages
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1457G–AVR–09/03
ATmega323(L)
Figure 5. The ATmega323 AVR Enhanced RISC Architecture
Data Bus 8-bit
16K X 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
2K x 8
Data
SRAM
1K x 8
EEPROM
32
I/O Lines
Interrupt
Unit
SPI
Unit
Serial
USART
Serial
TWI Bus
8-bit
Timer/Counter
with PWM
16-bit
Timer/Counter
with PWM
8-bit
Timer/Counter
with PWM
Watchdog
Timer
A/D Converter
MUX and Gain
Analog
Comparator
The AVR uses a Harvard architecture concept – with separate memories and buses for
Program and Data. The Program memory is executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the Pro-
gram memory. This concept enables instructions to be executed in every clock cycle.
The Program memory is In-System Reprogrammable Flash memory.
With the jump and call instructions, the whole 16K address space is directly accessed.
Most AVR instructions have a single 16-bit word format. Every Program memory
address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section (512
to 4K bytes, see page 177) and the Application Program section. Both sections have
dedicated Lock bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section is allowed only in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the Reset Routine (before subroutines
or interrupts are executed). The 12-bit Stack Pointer SP is read/write accessible in the
I/O space.
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