ATMEGA6450-16AI(2004) 데이터 시트보기 (PDF) - Atmel Corporation

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ATMEGA6450-16AI
(Rev.:2004)

8-bit Microcontroller with In-System Programmable Flash

Atmel Corporation 

ATmega325/3250/645/6450

AVR CPU Core

Introduction

Architectural Overview

This section discusses the AVR core architecture in general. The main function of the

CPU core is to ensure correct program execution. The CPU must therefore be able to

access memories, perform calculations, control peripherals, and handle interrupts.

Figure 4. Block Diagram of the AVR Architecture

Flash

Program

Memory

Instruction

Register

Instruction

Decoder

Control Lines

Program

Counter

Data Bus 8-bit

Status

and Control

32 x 8

General

Purpose

Registrers

ALU

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

Data

SRAM

EEPROM

I/O Module1

I/O Module 2

I/O Module n

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture

– with separate memories and buses for program and data. Instructions in the program

memory are executed with a single level pipelining. While one instruction is being exe-

cuted, the next instruction is pre-fetched from the program memory. This concept

enables instructions to be executed in every clock cycle. The program memory is In-

System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with

a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)

operation. In a typical ALU operation, two operands are output from the Register File,

9

2570A–AVR–09/04

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