AWC6323 데이터 시트보기 (PDF) - ANADIGICS
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AWC6323 Datasheet PDF : 11 Pages
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AWC6323
APPLICATION INFORMATION
To ensure proper performance, refer to all related
Application Notes on the ANADIGICS web site:
http://www.anadigics.com
Shutdown Mode
The power amplifier may be placed in a shutdown
mode by applying logic low levels (see Operating
Ranges table) to the VENABLE and VMODE voltages.
Bias Modes
The power amplifier may be placed in Low, Medium or
High Bias modes by applying the appropriate logic level
(see Operating Ranges table) to the VMODE1, and VMODE2
pins. The Bias Control table lists the recommended
modes of operation for various applications.
Vcontrols
Venable/Vmode(s)
On Sequence Start
T_0N =0µ
ON Sequence
Rise/Fall Max 1µS
Defined at 10% to 90%
of Min/Max Voltage
Off Sequence Start
T_0FF= 0µ
OFF Sequence
RFIN_CELL,PCS
notes 1,2
VEN_CELL,PCS
VCC, VCCA
note 1
T_0N+1µS
T_0N+3 µS
T_0FF+2µS T_0FF+3µS
Referenced After 90% of Rise
Time
Referenced Before10% of Fall
Time
Figure 3: Recommended ON/OFF Timing Sequence
Notes:
(1) Level might be changed after RF is ON.
(2) RF OFF defined as PIN ≤ -30 dBm.
(3) Switching simultaneously between VMODE and VEN is not recommended.
APPLICATION
Table 6: Bias Control
POUT
LEVELS
BIAS
MODE
VEN
VMODE1
VMODE2
VCC
CDMA - low power
(Low Bias Mode)
CDMA - med power
(Medium Bias Mode)
CDMA - high power
(High Bias Mode)
Shutdown
< +10 dBm Low +1.8 V
-
0V
> 8 dBm
< +16 dBm
Med
+1.8 V +1.8 V +1.8 V
> +16 dBm High +1.8 V 0 V +1.8 V
-
Shutdown 0 V
0V
0V
3.2 - 4.2 V
3.2 - 4.2 V
3.2 - 4.2 V
3.2 - 4.2 V
8
Data Sheet - Rev 2.2
03/2012
VBATT
> 3.2 V
> 3.2 V
> 3.2 V
> 3.2 V
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