AZ100EL32 데이터 시트보기 (PDF) - Unspecified
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AZ100EL32 Datasheet PDF : 6 Pages
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AZ10EL32
AZ100EL32
ARIZONA MICROTEK, INC.
ECL/PECL ÷ 2 Divider
FEATURES
• 510ps Propagation Delay
• 3.0GHz Toggle Frequency
• High Bandwidth Output Transitions
• 75kΩ Internal Input Pulldown Resistors
• Direct Replacement for ON Semiconductor
MC10EL32 & MC100EL32
PACKAGE AVAILABILITY
PACKAGE
SOIC 8
SOIC 8 T&R
SOIC 8 T&R
SOIC 8
SOIC 8 T&R
SOIC 8 T&R
TSSOP 8
TSSOP 8 T&R
TSSOP 8 T&R
TSSOP 8
TSSOP 8 T&R
TSSOP 8 T&R
PART NO.
AZ10EL32D
AZ10EL32DR1
AZ10EL32DR2
AZ100EL32D
AZ100EL32DR1
AZ100EL32DR2
AZ10EL32T
AZ10EL32TR1
AZ10EL32TR2
AZ100EL32T
AZ100EL32TR1
AZ100EL32TR2
MARKING
AZM10EL32
AZM10EL32
AZM10EL32
AZM100EL32
AZM100EL32
AZM100EL32
AZTEL32
AZTEL32
AZTEL32
AZHEL32
AZHEL32
AZHEL32
DESCRIPTION
The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of
multiple EL32’s in a system.
The EL32 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For
single-ended input applications, the VBB reference should be connected to one side of the CLK/¯C¯L¯K¯ differential input
pair. The input signal is then fed to the other CLK/¯C¯L¯K¯ input. The VBB pin should be used only as a bias for the
EL32 as its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01µF
capacitor.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION
PIN
CLK, C¯L¯¯K
Reset
VBB
Q, Q¯
VCC
VEE
FUNCTION
Clock Inputs
Asynch Reset
Reference Voltage Output
Data Outputs
Positive Supply
Negative Supply
Reset 1
CLK 2
CLK 3
VBB 4
8 VCC
R
7Q
÷2
6Q
5 VEE
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
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