AZ100LVEL16VV(2012) 데이터 시트보기 (PDF) - Arizona Microtek, Inc
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AZ100LVEL16VV
(Rev.:2012)
(Rev.:2012)
Arizona Microtek, Inc
AZ100LVEL16VV Datasheet PDF : 9 Pages
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Arizona Microtek, Inc.
AZ100LVEL16VV
PIN DESCRIPTION AND CONFIGURATION
Dual Frequency PECL/ECL Oscillator
Gain Stage & Buffer with Enable
Table 1 - Pin Description AZ100LVEL16VTNA+
Pin
Name Type
Function
1
D0
Input
Data Input
2
D¯¯0
Input
Inverting Data Input
3
D1
Input
Data Input
4
D¯¯1
Input
Inverting Data Input
5
VBB
Output
6
NC
-
Reference Voltage
N/A
7
VEE
Power
8
NC
-
Negative Supply
N/A
9
EN
Input
Output Enable
10
Q¯ HG
Output High Gain Inverting PECL Output
11
QHG
Output
High Gain PECL Output
12
SEL
Input
Data Input Select
13
VCC
Power
Positive Supply
14
NC
-
N/A
15
Q
Output
PECL Output
16
Q¯
Output
Inverting PECL Output
Q Q NC VCC
16 15 14 13
D0 1
12 SEL
D0 2
D1 3
Leave Pad
Open or
Connect to
VEE
11 QHG
10 QHG
D1 4
9 EN
5678
VBB NC VEE NC
Figure 1 - Pin Configuration
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+1-480-962-5881
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May 2012, Rev 2.0
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