AZ12000K 데이터 시트보기 (PDF) - Arizona Microtek, Inc

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AZ12000K

Phase-Locked Loop Clock Generator

Arizona Microtek, Inc 

AZ12000

AZ12001

Loop Filter Design

The combination of the phase detector, amplifier, VCO and divider form a second-order phase-locked loop. Proper

selection of the loop components is important to obtain stable, low jitter operation.

The loop bandwidth (or natural frequency, ωn) and damping factor (ζ) are the two major driving forces that define the

loop’s response to a disturbance. The value of ζ is typically 0.7 to ensure the fastest step response consistent with no

ringing. However in many oscillator application ζ may be 3 or higher to provide further phase noise reduction. ωn is

chosen as a compromise between settling time, VCO jitter and reference feedthrough. These values can be computed by

the following equations:

ωn

=

1

N

Kφ KVCO

τ1

ζ = τ 2ωn

2

τ1 = R1C1

τ 2 = R2C1

Kφ = Phase Detector Gain (20.3 radians/V)

KVCO = VCO Gain (radians/sec/volt)

N = Frequency Divisor value (4,8, 16 or 32)

The component definitions are shown in the figure below. R3 should be equal to R1 to minimize integrator offsets.

C1

VCO

CONTROL

R1

R2

VOLTAGE

R3

CPREF CPOUT

INTREF INTSUM

INTOUT

INTEGRATOR

CHARGE

PUMP

Figure 2 Charge Pump and Integrator

January 2005 * REV - 3

www.azmicrotek.com

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