HMS39C7092 데이터 시트보기 (PDF) - Hynix Semiconductor

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HMS39C7092

Embedded Flash MCU

Hynix Semiconductor 

Flash MCU(HMS39C7092)

Figures

Figure 1.1 Package Outline........................................................................................ 14

Figure 1.2 HMS39C7092 Block Diagram .................................................................... 15

Figure 1.3 HMS39C7092 Memory Map....................................................................... 25

Figure 1.4 Memory Map of Mode 3............................................................................. 25

Figure 1.5 Memory Map of when Mode 4 and Mode 5 ................................................. 26

Figure 1.6 Memory Map of Mode 6 and Mode 7 .......................................................... 26

Figure 2.1 ARM7TDMI Core Block Diagram ................................................................ 29

Figure 2.2 ARM instruction set formats ....................................................................... 30

Figure 2.3 Register Organization in ARM state............................................................ 32

Figure 2.4 THUMB instruction set formats................................................................... 33

Figure 2.5 Register Organization in THUMB state ....................................................... 35

Figure 2.6 Mapping of THUMB state registers onto ARM state registers. ...................... 35

Figure 2.7 Program status register format ................................................................... 36

Figure 3.1 Block Diagram of the Bus Controller ........................................................... 48

Figure 3.2 Access Area Map for Each Operating Mode................................................ 52

Figure 3.3 Access Size and Data Alignment Control (8-Bit Access Area) ...................... 54

Figure 3.4 Access Size and Data Alignment Control (16-Bit Access Area) .................... 55

Figure 3.5 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Word Access) ................ 56

Figure 3.6 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Word Access)................ 56

Figure 3.7 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Half-word Access).......... 57

Figure 3.8 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Half-word Access).......... 57

Figure 3.9 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Byte Access).................. 58

Figure 3.10 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Byte Access)................ 58

Figure 3.11 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Word Access)............... 59

Figure 3.12 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Word Access) .............. 59

Figure 3.13 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Half-Word Access)........ 60

Figure 3.14 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Half-Word Access) ....... 60

Figure 3.15 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Byte Access)................ 61

Figure 3.16 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Byte Access)................ 61

Figure 3.17 Example of Wait State Insertion Timing. .................................................... 62

Figure 3.18 Example of External Bus Master Operation............................................... 64

Figure 5.1 PMU Block Diagram .................................................................................. 74

Figure 5.2 Reset and Power Management State Machine. ........................................... 76

Figure 5.3 Power on Reset Timing Diagram ................................................................ 81

Figure 5.4 Watch Dog Timer Overflow Timing Diagram ................................................ 81

Figure 5.5 Soft Reset (from WDT) Timing Diagram ...................................................... 82

Figure 5.6 Soft Reset (from PMU) Timing Diagram ...................................................... 82

Figure 6.1 Interrupt Control Flow Diagram .................................................................. 84

Figure 7.1 Watchdog Timer Module Block Diagram ..................................................... 92

Figure 7.2 Operation in the Watchdog Timer Mode ...................................................... 94

Figure 7.3 Operation in the Interval Timer Mode .......................................................... 95

Figure 7.4 Interrupt Clear in the Interval Timer Mode ................................................. 100

Figure 7.5 Interrupt Clear in the Watchdog Timer Mode with Reset Disable................. 101

Figure 7.6 Interrupt Clear in the Watchdog Timer Mode with Power-on Reset.............. 102

Figure 7.7 Interrupt Clear in the Watchdog Timer Mode with Manual Reset ................. 103

Figure 8.1 General-purpose Timer Unit Module Block Diagram .................................. 106

Preliminary

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