SY100E431JCTR 데이터 시트보기 (PDF) - Micrel
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SY100E431JCTR Datasheet PDF : 4 Pages
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Micrel, Inc.
3-BIT DIFFERENTIAL
FLIP-FLOP
SY10E431
SY1S0YE14003E1431
SY100E431
FEATURES
s Differential D, clock and Q
s Extended 100E VEE range of –4.2V to –5.5V
s VBB output for single-ended use
s 1100MHz min. toggle frequency
s Edge-triggered asynchronous set and reset
s Fully compatible with Motorola MC10E/100E431
s Available in 28-pin PLCC package
BLOCK DIAGRAM
S0
D0
D0
CLK0
CLK0
R0
S1
D1
D1
CLK1
CLK1
R1
S2
D2
D2
CLK2
CLK2
R2
S
DQ
Q0
Q
Q0
R
S
DQ
Q1
Q
Q1
R
S
DQ
Q2
Q
Q2
R
VBB
DESCRIPTION
The SY10/100E431 are 3-bit flip-flops with differential
clock, data input and data output.
The asynchronous Set and Reset controls are edge-
triggered rather than level controlled. This allows the user
to rapidly set or reset the flip-flop and then continue
clocking at the next clock edge without the necessity of
de-asserting the set/reset signal (as would be the case
with a level controlled set/reset).
The E431 is also designed with larger internal swings,
an approach intended to minimize the time spent crossing
the threshold region and thus reduces the metastability
susceptibility window.
PIN NAMES
Pin
D[0:2], D[0:2]
CLK[0:2], CLK[0:2]
S[0:2]
R[0:2]
VBB
Q[0:2], Q[0:2]
VCCO
Function
Differential Data Inputs
Differential Clock Inputs
Edge Triggered Set Inputs
Edge Triggered Reset Inputs
VBB Reference Output
Differential Data Outputs
VCC to Output
TRUTH TABLE(1)
Dn
CLKn
Rn
Sn
Qn
L
Z
L
L
L
H
Z
L
L
H
X
L
Z
L
L
X
L
L
Z
H
NOTE:
1. Z = LOW-to-HIGH transition.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
1
Rev.: E Amendment: /0
Issue Date: March 2006
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