BD19915MUV 데이터 시트보기 (PDF) - ROHM Semiconductor

부품명

상세내역

제조사

BD19915MUV

Silicon monolithic IC

ROHM Semiconductor 

4/4

○Notes on use

1. Notes for printed pattern board

・PVCC1, PVCC2, AVCC and CSWI must be connected to power supply on the board.

・PGND1, PGND2, PGND3 and AGND must be connected to GND on the board.

・Please wire with wide, short and keep low impedance for the PVCC1, PVCC2 and AVCC connection.

・Please wire with wide, short and keep low impedance for the PGND1, PGND2, PGND3 and AGND connection.

・Please extract the output of DC-to-DC converter from both ends of capacitor connected to VDCO1, VDCO2 and VDCO3.

・The characteristics of DC-to-DC converter is influenced by surrounding, components and board pattern design. Consider the

effects from surroundings while designing.

2. Notes for external parts

・Use low ESR ceramic capacitor between PVCC1(PVCC2) and PGND1(PGND2). Place the capacitor right next to the IC pins.

・Please wire AGND independently from the GND side of bi-pass capacitor.

・Please use parts recommended by this specification and place external parts such as inductors and capacitors right next to the IC pins.

Especially, please use wide and short wire in the part where a large current flows.

3. Notes for SELDCO1 terminal, SELSQ terminal and SELRST terminal

・Please connect these terminal to the power supply or GND, and prohibit switching it after turning on the power supply

(IC in operation).

4. Notes for Thermal shutdown function

・Thermal shutdown function is activated by the chip temperature achieving 175℃ (typ.). And DC-to-DC converter output will

be turned off (DCSW1=DCSW2=0.0V, DCSW3=VCC).

・Main purpose of TSD is to shutting IC down from runaway effect. It is not to compensate or to protect set device. Therefore,

please do not continuously operate the IC after TSD circuit is activated and/or premise operations such that TSD circuit function

being used.

5. Notes for Over-voltage mute function

・Over-voltage mute function is built in this IC. DC-to-DC converter output is turned off (DCSW1=DCSW2=0.0V, DCSW3=VCC) when the VCC

becomes 6.5V (typ.) or higher.

6. Notes for Over current protection function

・Over-current protection circuit is built in to Each outputs terminal except VDCO3 and XRESET. Which protects IC from destruction by

abrupt VCC and GND short.

7. Notes for load current while start-up

・Keep light Load at each output while start-up.

8. Notes for Absolute maximum ratings

・Even quality control of the product have fun well taken care, however operating above the absolute maximum ratings of supply

voltage and/or operational temperature range may cause decay and destroy the IC. Please make it sure to use the IC within

the operating rage at anytime while designing.

・Operating over the maximum ratings of supply voltage and/or operational temperature may destroy the product. Once destroyed,

open/short mode to specify the defection is impossible. Please have physical countermeasure such as adding fuse etc. If specific mode

such that exceeding the Absolute Maximum ratings is expected.

9. Notes for Terminal to Terminal short / miss-alignment

・While mounting IC on the board, check direction and shift of the IC. If inadequately mounted, IC might destroy.

・Avoid short-circuit of I/O terminals (VDCO1, VDCO2, VDCO3, DCSW1, DCSW2, DCSW3) and VCC / GND.

If short-circuit of terminals and VCC /GND is executed, the IC will break down and the smoke may occur.

10. Notes for test of mounted print board

・While connecting capacitor to Low impedance pins, please discharge capacitor by one process by another to prevent stressing the IC.

While mounting and removing the IC to/from the Board in the inspection process, be sure to turn off the power supply at each actions.

Moreover equip ground earth in assembling process for ESD protection and handle with care during the test and/or transportation.

11. Notes for input terminal

・This IC is a monolithic IC, and has P+ isolation and P substrate for the element separation. Therefore, a parasitic PN junction is firmed in

this P-layer and N-layer of each element. For instance, the resistor or the transistor is connected to the terminal as shown in the figure

below. When the GND voltage potential is greater than the voltage potential at Terminals A or B, the PN junction operates as a parasitic

diode. In addition, the parasitic NPN transistor is formed in said parasitic diode and the N layer of surrounding elements close to said

parasitic diode. These parasitic elements are formed in the IC because of the voltage relation. The parasitic element operating causes

the wrong operation and destruction. Therefore, please be careful so as not to operate the parasitic elements by applying lower voltage

than GND (P substrate) to input terminals. Moreover, please apply each input terminal with lower than the power-supply voltage or

equal to the specified range in the guaranteed voltage when the power-supply voltage being applied.

12. Notes for ASO

・Set up the current so as the output transistor not to exceed absolute maximum ratings and ASO while operating the IC.

13. Notes for Thermal design

・In order to build sufficient margin into the thermal design, give proper consideration to the allowable loss (Power Dissipation) in

actual operation.

REV. A

Share Link: