BD8105FV 데이터 시트보기 (PDF) - ROHM Semiconductor
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BD8105FV Datasheet PDF : 13 Pages
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BD8105FV
●INPUT SIGNAL’S TIMING CHART
50%
CLK
TSESTTSEHD
50%
SERIN
TSEW
LATCH
Technical Note
TCK
TCKH
TCKL
TLADZ
50% TLAH
Fig.16
●INPUT SIGNAL’S TIMING RULE（Ta=-40～105℃ Vcc=4.5～5.5V）
Parameter
Symbol
Min
Unit
CLK period
TCK
1000
ns
CLK high pulse width
TCKH
480
ns
CLK low pulse width
TCKL
480
ns
SERIN high and low pulse width
TSEW
980
ns
SERIN setup time prior to CLK rise
TSEST
150
ns
SERIN hold time after CLK fall
TSEHD
150
ns
LATCH high pulse time
TLAH
480
ns
Last CLK rise to LATCH rise
TLADZ
250
ns
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8/12
2009.07 - Rev.B
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