BIT3193 데이터 시트보기 (PDF) - Unspecified
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BIT3193 Datasheet PDF : 10 Pages
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Beyond Innovation Technology Co., Ltd.
BIT3193
Table 4
Parameter
Test Conditions
Supply Voltages
Pin VDD input
Chip Consumed Current
8V Supply Voltage
Ta=25°C
Error Amplifier Reference Voltage
Non-Inverting
amplifier
input
of
the
error Measure INN
Line regulation
VDD=4.0~13.2 V
Under Voltage Look Out
Min.
4.0
1.2125
Positive Going Threshold
Ta=25°C
3.8
Hysteresis
Note3
0.1
High Frequency Ramp Wave Generator
Operating Frequency
50
Output peak(CTOSC)
Note1
Output valley(CTOSC)
Error Amplifier
Input voltage
0.1
Open loop gain
Note2
60
Unit gain band width
1
Power On Initialization and Latched Off Protection Enable
Pin TIMER Output current
Case1. TIMER <0.3V
Pin TIMER Output current
Case1. TIMER > 0.3V
VDD=12V, Ta=25°C
Power On Reset/Initialization Note 3
threshold on pin TIMER
Latched Off Protection enable
threshold on pin TIMER
Open Load Detection
Pin ISEN open
lower threshold
load
detection VDD=12V, Ta=25°C
Hysterisis
Over Voltage Detection and Clamping
Pin CLAMP over voltage detection
lower threshold
Hysterisis
VDD=12V, Ta=25°C
INN pin pull-up current source
Low Frequency PWM Generator
Ramp Wave Peak(CTPWM)
Ramp Wave Valley(CTPWM)
PWM Frequency
10
Control voltage of 0 % Duty cycle
on pin PWMDC
Case 1. MODSEL = 0V
Control voltage of 0 % Duty cycle VDD=12V, Ta=25°C
on pin PWMDC
Case 1. MODSEL = ICVDD
Output voltage of Pin PWMOUT
for making the logic “high”.
Pin PWMOUT output for making
the logic “low”
Maximum Duty Cycle
Output
CMOS output impedance
(Note2, Note3)
Rising Time
Falling Time
VDD=12V,
2000pF(Note2,
Note3)
Delay Time
Typ.
4
1.25
2
4.0
0.2
2.25
0.5
80
1.5
20
1
0.3
2.5
1.3
20
2.0
20
60
2.5
1.0
1.0
2.5
2.5
Floating
92
50
110
100
200
Max.
8
1.2875
20
4.2
0.3
400
3
100K
Unit
V
mA
V
mV
V
V
KHz
V
V
V
dB
MHz
uA
uA
V
V
V
mV
V
mV
uA
V
V
Hz
V
V
V
%
ohm
nS
nS
nS
04/11/08
Confidential, for authorized user only
page 6 of 10
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