Ϟ⍋䋱ኁⷑ߯ᖂ⬉ᄤ᳝䰤݀ৌ
Shanghai Belling-Systron Microelectronics Co., Ltd.
ԡᏺ57&ⱘ0$6.ऩ⠛ᴎ㢃⠛%/
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset
PORTA $00
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 unaffected
3.2.2 B ࣇޗӉ୶ PORTBďPort B Data RegisterĐ
PORTB ᰃ B ষᰃ᭄ᆘᄬ఼ˈ↣ϔԡᇍᑨ I/O ষ PB7:PB0 ЁⱘϔϾDŽᔧ I/O ষЎ䕧ܹ
⢊ᗕᯊ䇏 PORTB Ⳍᑨⱘԡৃҹ߸ᮁ I/O ষⱘ⬉ᑇ䘏䕥˗ᔧ I/O ষЎ䕧ߎ⢊ᗕᯊ ݭPORTB Ⳍ
ᑨⱘԡৃҹࠊ I/O ষⱘ⬉ᑇ䘏䕥DŽ
Address bit 7 bit 6
PORTB $01 PB7 PB6
bit 5
PB5
bit 4
PB4
bit 3
PB3
bit 2
PB2
bit 1
PB1
bit 0
PB0
Reset
unaffected
3.2.3 C ࣇޗӉ୶ PORTCďPort C Data RegisterĐ
PORTC া᳝ PC0 䖭ϔԡˈ⫼Ѣࠊ OUT ⱘ䕧ߎ䘏䕥DŽOUT ᓩ㛮ᰃ৺ࡴ䕑 38KHz ⱘ䇗
ࠊֵো⬅ F38KE ᆘᄬ఼އᅮDŽ
Address bit 7 bit 6
PORTC $02
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0 Reset
PC0 unaffected
3.2.4 A ࣇֺޗӉ୶ DDRAďPort A Data Direction RegisterĐ
DDRA ⫼Ѣࠊ PA ষⱘ䕧ܹ䕧ߎᮍˈDDRAx˙0 ᯊˈPAx Ў䕧ܹ⢊ᗕ˗DDRAx˙1
ᯊˈPAx Ў䕧ߎ⢊ᗕDŽ
DDRA
Address
$04
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Reset
00000000
3.2.5 B ࣇֺޗӉ୶ DDRBďPort B Data Direction RegisterĐ
DDRB ⫼Ѣࠊ PB ষⱘ䕧ܹ䕧ߎᮍˈDDRBx˙0 ᯊˈPBx Ў䕧ܹ⢊ᗕ˗DDRBx˙1
ᯊˈPBx Ў䕧ߎ⢊ᗕDŽ
DDRB
Address
$05
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Reset
00000000
3.2.6 Շನ୶୶ TDRďTimer Data RegisterĐ
TDR ᰃϔϾৃ䇏 ⱘݭ8 ԡᆘᄬ఼ˈᅗⱘݙᆍᰃ 8 ԡᅮᯊ఼䅵఼᭄ⱘᔧࠡؐDŽ䇏䆹ᆘᄬ
఼ᯊϡӮᕅડᅮᯊ఼ⱘᎹDŽ
Address bit 7 bit 6
TDR $08 TD7 TD6
bit 5
TD5
bit 4
TD4
bit 3
TD3
bit 2
TD2
bit 1
TD1
bit 0
TD0
Reset
11111111
3.2.7 Շನ୶ࣅᄥޗӉ୶ TCRďTimer Control RegisterĐ
TCR ⫼Ѣᇍ 8 ԡᅮᯊ఼䖯㸠䆒ᅮDŽ
⬉䆱˖Ӵⳳ˖㔥ഔZZZV\VWURQVKFQRI