BL7442LV 데이터 시트보기 (PDF) - Shanghai Belling Co., Ltd.
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BL7442LV Datasheet PDF : 10 Pages
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Function Description
Block Diagram
Main
memory
255
EEPROM
256X8
32
31 Area for
permanent
data storage
0
Address Data
BL7442LV Low voltage
Intelligent 2K bits EEPROM
Protection
memory
31
0
Address
Data
Security memory
3
REF data
2
REF data
PSC
1
REF data
0
EC
Address
Data
Memory
Main/Protection
Security
85
2LSB
HV Generator
Current
Generator
Decoder
Column
Sampling
Add. Data
Register, Comparator
Program
Control
Reset
Block Logic
Sequencer
And
Security
Logic
Interface
VCC GND
I/O RST CLK
Figure 2
The BL7442LV consists of 256 x 8 bit EEPROM main memory (figure 2) and a 32-bit protection-
memory With PROM functionality .The main memory is erased and written byte by byte. When erased, all
8 bits of a data byte are set to logical one. When written, the information in the individual EEPROM cells is
to the input data, altered bit by bit to logical zeros (logical AND between the old and the new data in the
EEPROM).
Normally a data change consists of an erase and write procedure. It depends on the contents of the
data byte in the main memory and the new data byte whether the EEPROM is really erased and/or written.
If none of the 8 bits in the addressed byte requires a zero-to-one transition the erase access will be
suppressed. Vice versa the write access will be suppressed if no one-to-zero transition is necessary. The
write and the erase operation takes at least 2.5 ms each. The first 32 bytes can be irreversibly protected
against data change by writing the corresponding bit in the protection memory. Each data byte in this
address range is assigned to one bit of the protection memory and has the same address as the data byte in
the main memory which it is assigned to. Once written the protection bit cannot be erased.
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Total 10 Pages
8/16/2006
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