BR24C21 데이터 시트보기 (PDF) - ROHM Semiconductor

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BR24C21

EDID Memory (For display)

ROHM Semiconductor 

BR24C21xxx Series (1K)

●Synchronous data timing

tR

tF

t HI GH

SCL

SDA

(IN)

SDA

(OUT)

tHD:STA

tBUF

tSU:DAT

tLOW

tPD

tHD:DAT

Datasheet

SCL

SDA

D0

ACK

WRITE DATA(n)

tWR

STOP CONDITION START CONDITION

Figure 2. Write Cycle Timing

START BIT STOP BIT

SCL

tSU:STA

SDA

tHD:STA

tSU:STO

SCL

SDA

START BIT

STOP BIT

Figure 1. Synchronous Data Timing

VCLK

・SDA data is latched into the chip at the rising edge of the SCL clock.

・Output data toggles at the falling edge of the SCL clock.

tVSU

WRITE COMMAND tVHD

Figure 3. Write Enable Timing

●Transmit-only mode

・After power is on, the BR24C21/F/FJ/FV is in Transmit-Only Mode. In this mode data can be output by providing the clock

to the VCLK pin.

・When the power is on, the SCL pin needs to be set to VCC(High level).

・SDA is at high-impedance during input of the first 9 clocks. At the 10th rising clock edge of VCLK data is output. After

power on, the output data is as follows:

00h address data → 01h address data → 02h address data → …

The address is incremented by one, after every 9 clocks of VCLK. All addresses are output in this mode.

When the counter reaches the last address, the next output data is 00h address data. (See Figure 4.)

・In this mode, the NULL bit (High data) is output between the address data and the next address data. (See Figure 5.)

・The read operation is in Transmit-Only Mode and can be started after the power is stabilized.

Vcc

SCL

1

VCLK

ｔVPU

SDA

9 10

D7 D6 D5 D4 D3

00h ADDRESS DATA

Figure 4. Transmit Only Mode

VCLK

SDA

tVPD

D1

ADDRESS n

DATA

tVHIGH tVLOW

D0

D7

D6

NULL BIT

DATA=1

ADDRESS n+1

DATA

Figure 5. Null Bit

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© 2012 ROHM Co., Ltd. All rights reserved.

TSZ22111・15・001

4/18

TSZ02201-0R2R0G100270-1-2

10.Jul.2012 Rev.001

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