BR24C21 데이터 시트보기 (PDF) - ROHM Semiconductor
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BR24C21 Datasheet PDF : 21 Pages
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BR24C21xxx Series (1K)
Datasheet
○Random Read
The Random read operation allows the Master to access any memory location. This operation involves a two-step
process. First, the Master issues a Write command that includes the START condition and the Slave address field (with
R/W set to “0”) followed by the word address of the word to be read. This procedure sets the internal address counter of
the BR24C21/F/FJ/FV to the desired address. After the word address Acknowledge is received by the Master, the
Master immediately re-issues a START condition followed by the Slave address field with R/W set to “1.” The device will
respond with an Acknowledge and then transmit the 8-data bits stored at the addressed location. If the Master does not
acknowledge the transmission but does generate the STOP condition, the IC will discontinue transmission.
SDA
LINE
S
W
S
T
R
T
R
S
A
I
A
E
T
R
SLAVE
T
WORD
R
SLAVE
A
O
T
ADDRESS
E
ADDRESS（ｎ）
T
ADDRESS
D
DATA(n)
P
1010***
*
WA
6
RA
/C
WK
WA
0
1010***
D7
A
RA
C
/C
K
WK
D0
A
C
K
*:Don’t care
Figure 11. Random Read Cycle Timing
○Sequential Read
･If the Master does not transfer an Acknowledge and does not generate a STOP condition during the current Read
operation, the BR24C21/F/FJ/FV continues to output the next address data in sequence. For Read operations, all bits
in the address counter are incremented, allowing the entire array to be read during a single operation. When the
counter reaches the top of the array, it will “roll over” to the bottom of the array and continue to transmit data.
･If the Master does not acknowledge the transmission but does generate a STOP condition, at this point the device
discontinues transmission.
･The sequential Read operation can be performed with both Current Read and Random Read.
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA(n)
1010***
D7
D0
RA
A
/C
C
WK
K
S
T
DATA(n+x)
O
P
D7
D0
A
A
C
C
K
*:Don’t care K
Figure 12. Sequential Read Cycle Timing
(Current Read)
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
7/18
TSZ02201-0R2R0G100270-1-2
10.Jul.2012 Rev.001
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