LCX016AM
2. Clock timing conditions (Ta = 25°C)
(MAC17 mode: fHCKn = 4.8MHz, fVCK = 24.9kHz)
Item
Symbol Min.
HST
HCK
Hst rise time
Hst fall time
Hst data set-up time
Hst data hold time
Hckn rise time∗4
Hckn fall time∗4
Hck1 fall to Hck2 rise time
trHst
—
tfHst
—
tdHst
—
thHst
—
trHckn
—
tfHckn
—
to1Hck –15
Hck1 rise to Hck2 fall time
Vst rise time
Vst fall time
VST
Vst data set-up time
Vst data hold time
Vck rise time
VCK
Vck fall time
Enb rise time
Enb fall time
ENB
Vck rise/fall to Enb rise time
Enb pulse width
Pcg rise time
Pcg fall time
PCG
Pcg fall to Vck rise/fall time
Pcg pulse width
Blk rise time
Blk fall time
BLK∗5
Blk fall to Vst rise time
Blk pulse width
to2Hck –15
trVst
—
tfVst
—
tdVst
—
thVst
—
trVck
—
tfVck
—
trEnb
—
tfEnb
—
tdEnb
—
twEnb
—
trPcg
—
tfPcg
—
toVck
—
twPcg
—
trBlk
—
tfBlk
—
toVst
—
twBlk
—
∗4 Hckn means Hck1 and Hck2.
∗5 Blk is the timing during SVGA mode (fHckn = 4.0MHz, fVck = 24.0kHz).
Typ.
—
—
50
50
—
—
0
0
—
—
10
10
—
—
—
—
500
2500
—
—
1000
1200
—
—
33
21
Max. Unit
30
30
—
—
30
ns
30
15
15
100
100
—
µs
—
100
100
100
100
—
—
ns
30
30
—
—
100
100
—
µs
—
–6–