SY87701LHI(2000) 데이터 시트보기 (PDF) - Micrel
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SY87701LHI Datasheet PDF : 12 Pages
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Micrel
PIN CONFIGURATION
VCCA 1
LFIN 2
DIVSEL1 3
RDINP 4
RDINN 5
FREQSEL1 6
REFCLK 7
FREQSEL2 8
FREQSEL3 9
N/C 10
PLLSP 11
PLLSN 12
GND 13
GND 14
Top View
SOIC
Z28-1
28 VCC
27 CD
26 DIVSEL2
25 RDOUTP
24 RDOUTN
23 VCCO
22 RCLKP
21 RCLKN
20 VCCO
19 TCLKP
18 TCLKN
17 CLKSEL
16 PLLRP
15 PLLRN
SY87701L
32 31 30 29 28 27 26 25
NC 1
RDINP 2
RDINN 3
FREQSEL1 4
REFCLK 5
FREQSEL2 6
FREQSEL3 7
NC 8
Top View
EP-TQFP
H32-1
24 RDOUTP
23 RDOUTN
22 VCCO
21 RCLKP
20 RCLKN
19 VCCO
18 TCLKP
17 TCLKN
9 10 11 12 13 14 15 16
PIN DESCRIPTIONS
INPUTS
RDINP, RDINN [Serial Data Input] Differential PECL.
These built-in line receiver inputs are connected to the
differential receive serial data stream. An internal receive
PLL recovers the embedded clock (RCLK) and data
(RDOUT) information. The incoming data rate can be within
one of eight frequency ranges depending on the state of
the FREQSEL pins. See “Frequency Selection” Table.
FREQSEL1, ..., FREQSEL3 [Frequency Select] TTL
Inputs.
These inputs select the output clock frequency range as
shown in the “Frequency Selection” Table.
DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs.
These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in the “Reference Frequency Selection” Table.
REFCLK [Reference Clock] TTL input.
This input is used as the reference for the internal
frequency synthesizer and the “training” frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN inputs.
CLKSEL [Clock Select] TTL Input.
This input is used to select either the recovered clock of
the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs.
CD [Carrier Detect] PECL Input.
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW the
data on the inputs RDIN will be internally forced to a constant
LOW, the data outputs RDOUT will remain LOW, the Link
Fault Indicator output LFIN forced LOW and the clock
recovery PLL forced to lock onto the clock frequency
generated from REFCLK.
OUTPUTS
LFIN [Link Fault Indicator] TTL Output.
This output indicates the status of the input data stream
RDIN. Active HIGH signal is indicating when the internal
clock recovery PLL has locked onto the incoming data
stream. LFIN will go HIGH if CD is HIGH and RDIN is within
the frequency range of the Receive PLL (1000ppm). LFIN
is an asynchronous output.
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