PDM34089SA10QTR 데이터 시트보기 (PDF) - Paradigm Technology

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PDM34089SA10QTR

3.3V 64K x 32 Fast CMOS Synchronous Static RAM with Burst Counter

Paradigm Technology 

PRELIMINARY

PDM34089

ADSP Write Timing Diagram

CLK

ADSP

tS tH

1

tW

tW

tCYC

2

ADSC

3

E

Address

Valid

4

A0-A14

BWE, GW

BW1-BW4

5

ADV

OE

6

Write Data

DQ1-DQ32

DQP1-DQP4

tS tH

Valid

Valid

Valid

Valid

7

A1, A0

A1, A0

A1, A0

A1, A0

8

NOTES:

1. E is low when CE = low, CE2 = high and CE2 = low. E is high otherwise.

2. BWx and GW are ignored for the first cycle when ADSP initiates the burst. ADSP active loads a new address into the address-

counter and forces the first cycle to be a read cycle.

3. OE is high before data input setup.

9

10

11

12

Rev 1.1 - 5/01/98

11

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