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PDM34089SA10QTR 데이터 시트보기 (PDF) - Paradigm Technology

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PDM34089SA10QTR Datasheet PDF : 15 Pages
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PRELIMINARY
PDM34089
3.3V 64K x 32 Fast CMOS
Synchronous Static RAM
1 with Burst Counter
Features
n Interfaces directly with the x86, Pentium™, 680X0
and PowerPC™ processors
n Single 3.3V power supply
n Mode selectable for interleaved or linear burst:
Interleaved for x86 and Pentium
Linear for 680x0 and PowerPC
n Fast access times:
9, 10, 12 and 15 ns
n High-density 64K x 32 architecture with burst
address counter
n Fully registered inputs
n High-output drive: 30 pF at rated TA
n Asynchronous output enable
n Self-timed write cycle
n Separate byte write enables and one global write
enable
n Internal burst read/write address counter
n Internal registers for address, data, controls
n Burst mode selectable
n Sleep mode
n Packages:
100-pin QFP - (Q)
100-pin TQFP - (TQ)
Description
2
The PDM34089 is a 2,097,152 bit synchronous ran-
dom access memory organized as 65,536 x 32 bits. It
3 is designed with burst mode capability and interface
controls to provide high-performance in second
level cache designs for x86, Pentium, 680x0, and
PowerPC microprocessors. Addresses, write data
4 and all control signals except output enable are con-
trolled through positive edge-triggered registers.
Write cycles are self-timed and are also initiated by
the rising edge of the clock. Controls are provided to
5 allow burst reads and writes of up to four words in
length. A 2-bit burst address counter controls the
two least-significant bits of the address during burst
reads and writes. The burst address counter selec-
6 tively uses the 2-bit counting scheme required by the
x86 and Pentium or 680x0 and PowerPC micropro-
cessors as controlled by the mode pin. Individual
write strobes provide byte write for the four 8-bit
bytes of data. An asynchronous output enable sim-
plifies interface to high-speed buses.
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TM i486, Pentium are trademarks of Intel Corp. PowerPC is a trademark of the International Business Machines Corporation.
Rev 1.1 - 5/01/98
1

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