PDM34088SA10QA 데이터 시트보기 (PDF) - Paradigm Technology

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PDM34088SA10QA

3.3V 64K x 32 Fast CMOS Synchronous Static RAM with Burst Counter and Output Register

Paradigm Technology 

Read Timing Diagram

PRELIMINARY

PDM34088

tCYC

CLK

tADSS

tCL

tCH

ADSP

tADSH

ADSC

tAS

ADDRESS

A1

A2

A3

tAH

tAAS

ADV

GW, BWE

BW4-BW1

CE

tCES

tCEH

tAAH

tWS

tWH

tCZ

tOE

OE

tOLZ

tOHZ

tCQ

tCZ

DATAOUT

Q1A1

Q1A2 Q2 A2

tCQX

Q3 A3

Q3 A2 Q4 A2 Q2 A2

NOTES: 1. Qn(A2) refers to output from address A2. Q1–4 refers to outputs according to burst sequence.

2. CE2 and CE2 have timing identical to CE. In this diagram, when CE is low, CE2 is low and CE2 is high. When CE is high,

CE2 is high and CE2 is low.

10

Rev 2.1 - 5/01/98

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