MU9C3640L-90TZC 데이터 시트보기 (PDF) - Music Semiconductors
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MU9C3640L-90TZC Datasheet PDF : 20 Pages
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LIST-XL
OPERATIONAL CHARACTERISTICS Continued
CAM Status
Validity bits at all memory locations
CAM/RAM Partitioning
Comparison Masking
Address register auto-increment or -decrement
Source and Destination Segment counters count ranges
Address register and Next Free Address register
Control register after reset (including CT15)
Persistent Destination for Command writes
Persistent Source for Command reads
Persistent Source and Destination for Data reads and writes
Configuration Register set
/RESET Condition
Skip = 0, Empty = 1 (empty)
64 bits CAM, 0 bits RAM
Disabled
Disabled
00B to 11B; loaded with 00B
Contains all 0s
Contains 0008H
Instruction decoder
Status register
Comparand register
Foreground
Table 4: Device Control State after Reset
Status Register
The 32-bit Status register, as shown in Table 10 on page 16,
is the default source for Command Read cycles. Bit 31 is
the internal Full flag, which will go LOW if there are no
empty memory locations. Bit 30 is the internal Multiple
Match flag, which will go LOW if a Multiple match was
detected. Bits 29 and 28 are the Skip and Empty Validity
bits, which reflect the validity of the last memory location
read. After a reset, the Skip and Empty bits will read 11 until
a read or move from memory has occurred. The rest of the
Status register down to bit 1 contains the address of the
Highest-Priority match. After a reset or a no-match
condition, the match address bits will be all 1s. Bit 0 is the
internal Match flag, which will go LOW if a match was found.
Comparand Register (CR)
The 64-bit Comparand register is the default destination for
data writes and reads, using the Segment Control register to
select which 16-bit segment of the Comparand register is to be
loaded or read out. The persistent source and destination for
data writes and reads can be changed to the mask registers or
memory by SPS and SPD instructions. During an automatic or
forced compare, the Comparand register is simultaneously
compared against the CAM portion of all memory locations
with the correct validity condition. Automatic compares always
compare against valid memory locations, while forced
compares, using CMP instructions, can compare against
memory locations tagged with any specific validity condition.
The Comparand register may be shifted one bit at a time to
the right or left by issuing a Shift Right or Shift Left
instruction, with the right and left limits for the wrap-around
determined by the CAM/RAM partitioning set in the Control
register. During shift rights, bits shifted off the LSB of the
CAM partition will reappear at the MSB of the CAM
partition. Likewise, bits shifted off the MSB of the CAM
partition will reappear at the LSB during shift lefts.
Mask Registers (MR1, MR2)
The Mask registers can be used in two different ways, either
to mask compares or to mask data writes and moves. Either
mask register can be selected in the Control register to
mask every compare, or selected by instructions to
participate in data writes or moves to and from Memory. If
a bit in the selected mask register is set to a 0, the
corresponding bit in the Comparand register will enter into
a masked compare operation. If a Mask bit is a 1, the
corresponding bit in the Comparand register will not enter
into a masked compare operation. Bits set to 0 in the mask
register cause corresponding bits in the destination register
or memory location to be updated when masking data writes
or moves, while a bit set to 1 will prevent that bit in the
destination from being changed.
Either the Foreground or Background MR1 can be set
active, but after a reset, the Foreground MR1 is active
by default. MR2 incorporates a sliding mask, where the
data can be replicated one bit at a time to the right or left
with no wrap-around by issuing a Shift Right or Shift
Left instruction. The right and left limits are determined
by the CAM/RAM partitioning set in the Control register.
For a Shift Right the upper limit bit is replicated to the
next lower bit, while for a Shift Left the lower limit bit is
replicated to the next higher bit.
THE MEMORY ARRAY
Memory Organization
The Memory array is organized into 64-bit words with each
word having an additional two validity bits (Skip and
Empty). By default, all words are configured to be 64
CAM cells. However, bits 8–6 of the Control register can
divide each word into a CAM field and a RAM field. The
RAM field can be assigned to the least-significant or
Rev. 2
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