IDT74FCT163543PF 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT74FCT163543PF Datasheet PDF : 7 Pages
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IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V IN
Pulse
Generator
6V
V CC
Open
V OUT
D.U.T.
GND
500Ω
50pF
500Ω
RT
CL
3250 drw 05
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
6V
GND
Open
DEFINITIONS:
3250 lnk 08
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
tSU
ETC.
tH
tREM
tH
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3250 drw 06
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
1.5V
tW
1.5V
3250 drw 07
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
tPHL
OPPOSITE PHASE
INPUT TRANSITION
ENABLE AND DISABLE TIMES
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
3250 drw 08
ENABLE
DISABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
6V
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
GND
3V
1.5V
0V
tPLZ
3V
3V
1.5V
tPHZ
0.3V VOL
1.5V
0.3V VOH
0V
0V
3250 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. If VCC is below 3V, input voltage swings should be adjusted not to
exceed VCC.
8.7
6
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