PI6C39911J 데이터 시트보기 (PDF) - Pericom Semiconductor Corporation

부품명

상세내역

제조사

PI6C39911J

3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer-SuperClock®

Pericom Semiconductor Corporation 

PI6C39911/PI6C39912

3.3V High Speed LVTTL or Balanced Output

11223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122P3344r5566o77g8899r00a1122m3344m556677a88b9900l11e2211S2233k44e5566w7788C990011l22o33c44k556677B8899u0011f22f33e44r5566-7788S99u0011p2211e22r33C4455l66o7788c99k0011®22

System

Clock

FB

REF

FS

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

TEST

REF

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

LOAD

L1

Z0

LOAD

L2

Z0

L3

LOAD

Z0

L4

FB

Z0

REF

FS

4F0

4Q0

4F1

4Q1

3F0

3Q0

3F1

3Q1

2F0

2Q0

2F1

2Q1

1F0

1Q0

1F1

1Q1

TEST

LOAD

LOAD

Figure 8. Board-to-Board Clock Distribution

Figure 8 shows the PI6C39911 connected in series to construct a zero

skew clock distribution tree between boards. Delays of the down

stream clock buffers can be programmed to compensate for the wire

length (i.e., select negative skew equal to the wire delay) necessary

to connect them to the master clock source, approximating a zero-

delay clock tree. Cascaded clock buffers will accumulate low-fre-

quency jitter because of the non-ideal filtering characteristics of the

PLL filter. It is recommended that not more than two clock buffers be

connected in series.

10

PS8497A 04/10/01

Share Link: