3291-11 데이터 시트보기 (PDF) - Peregrine Semiconductor
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3291-11
Peregrine Semiconductor
3291-11 Datasheet PDF : 15 Pages
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PE3291
Product Specification
Figure 2. Pin Configurations (Top View)
N/C 1
VDD 2
CP1 3
GND 4
fin1 5
Dec1 6
VDD1 7
fr 8
GND 9
foLD 10
20 VDD
19 VDD
18 CP2
17 GND
16 fin2
15 Dec2
14 VDD2
13 LE
12 Data
11 Clock
Figure 3. Package Type
20-lead TSSOP
Table 1. Pin Descriptions
Pin No. Pin Name Type
Description
1
N/C
No connect.
Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed
2
VDD
(Note 1) as close as possible to this pin and be connected directly to the ground plane.
3
CP1
Output
Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external
VCO.
4
GND
Ground.
5
fin1
Input
Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.2 GHz.
6
Dec1
Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and
be connected directly to the ground plane.
7
VDD1
PLL1 prescaler power supply (FlexiPower 1).
8
fr
Input
Reference frequency input.
9
GND
Ground.
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and
10
foLD
Output
data out of the shift register. CMOS output (see Table 11, foLD Programming Truth Table).
CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift
11
Clock
Input
register.
12
Data
Input
Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.
13
LE
Input
Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded
into one of the four appropriate latches (as assigned by the control bits).
14
VDD2
Output PLL2 prescaler power supply (FlexiPower 2).
15
Dec2
Output
Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and
be connected directly to the ground plane.
16
Fin2
Input
Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550 MHz.
17
GND
Ground.
18
CP2
Output
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external
VCO.
19
VDD
(Note 1) Same as pin 2.
20
VDD
(Note 1) Same as pin 2.
Note 1: VDD pins 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 15
Document No. 70-0009-04 │ UltraCMOS™ RFIC Solutions
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