PE3291-12 데이터 시트보기 (PDF) - Peregrine Semiconductor

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PE3291-12

1200 MHz / 550 MHz Dual Fractional-N FlexiPower™ PLL for Frequency Synthesis

Peregrine Semiconductor 

PE3291

Product Specification

PE3291 Description

The PE3291 is intended for such applications as

the local oscillator for the RF and first IF of dual-

conversion transceivers. The RF PLL (PLL1)

includes a 32/33 prescaler with a 1200 MHz

maximum frequency of operation, where the IF

PLL (PLL2) incorporates a 16/17 prescaler with a

550 MHz maximum frequency of operation. Using

an advanced fractional-N phase-locked loop

technique, the PE3291 can generate a stable,

very low phase-noise signal. The dual fractional

architecture allows fine resolution in both PLLs,

with no degradation in phase noise performance.

Data is transferred into the PE3291 via a three-

wire interface (Data, Clock, LE). Supply voltage

can range from 2.7 to 3.3 volts for VDD and from

0.8 to 3.3 volts for the FlexiPower supply. PE3291

features very low power consumption and is

available in a 20-lead TSSOP (JEDEC MO-153-

AC) package.

Figure 4. PE3291 Block Diagram

FlexiPower Operation

Each FlexiPower PLL prescaler can be supplied

its own dedicated supply voltage as low as 0.8

volts for substantial power savings. The maximum

frequency of operation scales with the FlexiPower

supply voltage. If voltages less than VDD are not

available, the FlexiPower supplies can be

internally generated, but the power savings will

not be as great as when using external

FlexiPower supplies.

Spurious Response

A critical parameter for synthesizer designs is

spurious output. Spurs occur at the integer

multiples of the step size away from center tone.

An important feature of fractional synthesizers is

their ability to reduce these spurious sidebands.

The PE3291 has a built-in method for reducing

these spurs, with no external components or

tuning required. In addition, this circuitry works

over the full commercial temperature range.

fin1

32/33

Prescaler

19-bit Fractional-N

Main Divider

Fractional Spur

Compensation

fr

Clock

Data

LE

Ref.

Amp.

9-bit Reference

Divider

21-bit Serial Control

Interface

Phase

Charge

CP1

Detector

Pump

Multiplexer

foLD

9-bit Reference

Divider

Phase

Charge

CP2

Detector

Pump

fin2

16/17

Prescaler

18-bit Fractional-N

Main Divider

Fractional Spur

Compensation

Document No. 70-0009-04 │ www.psemi.com

©2005 Peregrine Semiconductor Corp. All rights reserved.

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