MX98L715BEC 데이터 시트보기 (PDF) - Macronix International
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MX98L715BEC Datasheet PDF : 50 Pages
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MX98L715BEC
Pin Name Type Pin No
PAR
T/S 24
STOPB S/T/S 20
REQB
GNTB
T/S 115
I
114
EECS
O
59
BPA1
O
61
(EEDI)
BPA0
O
60
(EECK)
BPA[12:0] O
BPA13 O
(LED4)
BPA14 O
( LED0)
BPA15 O
( LED1)
BPA16 O
( LED2)
BPD0
T/S
(EEDO)
74-71,
68-60
77
78
79
80
58
BPD[7:0] T/S
FWEB T/S
( HLINKB)
FCSB
T/S
( VAUX)
FOEB
O
( LED3 )
RTX
O
PMEB O/D
51-58
69
70
81
102
110
128 Pin Function and Driver
PCI bus parity bit: shared PCI bus even parity bit for 32 bits AD bus and CBE
bus.
PCI Target requested transfer stop signal: as bus master, assertion of STOPB
cause MX98L715BEC either to retry, disconnect, or abort.
PCI bus request signal: to initiate a bus master cycle request
PCI bus grant acknowledge signal: host asserts to inform MX98L715BEC
that access to the bus is granted
EEPROM Chip Select pin.
Boot PROM address bit 1(EECS=0): together with BPA[15:0] to access
external boot PROM up to 256KB.
EEPROM data in(EECS=1): EEPROM serial data input pin.
Boot PROM address bit 0(EECS=0): together with BPA[15:0] to access
external boot PROM up to 256KB.
EEPROM clock(EECS=1): EEPROM clock input pin
Boot PROM address line.
Boot PROM address line 13 ( LED4 )
Boot PROM address line 14 (LED0)
Boot PROM address line 15 ( LED1)
Boot PROM address line 16 ( LED2)
Boot PROM data line 0(EECS=0): boot PROM or flash data line 0.
EEPROM data out(EECS=1): EEPROM serial data outpin(during reset
initialization).
Boot PROM data lines: boot PROM or flash data lines 7-0.
Flash Write Enable Output ( or Home PNA Link active low input )
Boot PROM Chip Select Output or Auxiliary Vdd input with 10k external
resistor pull-up. (Internal pull-down)
Boot PROM Output Enable ( LED3 )
Connecting an external resistor to ground, Resistor value=1K ohms
Power Management Event Status Output
P/N:PM0695
REV. 0.3, MAR. 30, 2001
5
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