MX98L715BEC 데이터 시트보기 (PDF) - Macronix International

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MX98L715BEC

3.3V SINGLE CHIP FAST ETHERNET NIC CONTROLLER

Macronix International 

MX98L715BEC

bit 24:Data Parity Report, is set to 1 only if PERR# active and PFCS<6> is also set.

bit 26-25:Device Select Timing of DEVSELB pin.

bit 27:not used

bit 28:Receive Target Abort, is set to indicate a transaction is terminated by a target abort.

bit 29:Receive Master Abort, is set to indicate a master transaction with Master abort.

bit 30:Signal System Error, is set to indicate assertion of SERRB.

bit 31:Detected Parity Error, is set whenever a parity error detected regardless of PFCS<6>.

5.1.3 PCI REVISION REGISTER ( PFRV ) ( Offset 0Bh-08h )

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Base Class

Subclass

Revision Number

Step Number

bit 3 - 0 : Step Number, range from 0 to Fh.

bit 7 - 4 : Revision Number, fixed to 6h for MX98L715BEC

bit 15 - 8 : not used

bit 23 - 16 : Subclass, fixed to 0h.

bit 31 - 24 : Base Class, fixed to 2h.

5.1.4 PCI LATENCY TIMER REGISTER ( PFLT ) (Offset 0Fh-0Ch)

PFLT Register (0Fh-0Ch)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Configuration Latency Timer

System cache line size

bit 0 - bit 7 : System cache line size in units of 32 bit word, device driver should use this value to program CSR0<15:14>.

bit 8 - bit 15 : Configuration Latency Timer, when MX98L715BEC assert FRAMEB, it enables its latency timer to

count.

If MX98L715BEC desserts FRAMEB prior to timer expiration, then timer is ignored. Otherwise, after timer expires,

MX98L715BEC initiates transaction termination as soon as its GNTB is deserted.

P/N:PM0695

REV. 0.3, MAR. 30, 2001

9

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