C167CS-L16M3V 데이터 시트보기 (PDF) - Infineon Technologies
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C167CS-L16M3V Datasheet PDF : 81 Pages
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C167CS-L16M3V
Low Power
Functional Description
The architecture of the C167CS-3V combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C167CS-3V.
Note: All time specifications refer to a CPU clock of 16 MHz
(see definition in the AC Characteristics section).
ProgMem
ROM
32 KByte
32
Instr. / Data
C166-Core
CPU
16
Data
16
Data
IRAM
Internal
RAM
3 KByte
XRAM
6+2 KByte
16
External Instr. / Data
PEC
Osc / PLL
XTAL
Interrupt Controller
16-Level
Priority
RTC WDT
16
CAN2
Interrupt Bus
Rev 2.0B active
16
Peripheral Data Bus
CAN1
Rev 2.0B active
ADC ASC0 SSC GPT PWM CCOM2 CCOM1
10-Bit (USART) (SPI)
T2
8
EBC
16+8
Channels
T3
T7
T0
T8
T1
XBUS Control
T4
External Bus
T5
16
8
Control
BRGen BRGen
T6
Port 0
Port 1
Port 5
Port 3
Port 7
Port 8
16
16
16
15
8
8
MCB04323_7CS
Figure 3 Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3).
The XBUS resources (XRAM, CAN) of the C167CS-3V can be individually enabled or
disabled during initialization. Register XPERCON selects the required modules which
are then enabled by setting the general X-Peripheral enable bit XPEN (SYSCON.2).
Modules that are disabled consume neither address space nor port pins.
Note: The default value of register XPERCON after reset selects 2 KByte XRAM and
module CAN1, so the default XBUS resources are compatible with the C167CR.
Data Sheet
14
V1.0, 2001-10
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