C8051F398 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F398

50 MIPS 16 kB Flash, 512B EEPROM Mixed-Signal MCU

Silicon Laboratories 

C8051F39x/37x

List of Figures

Figure 1.1. C8051F392/3/6/7/8/9 Block Diagram .................................................... 18

Figure 1.2. C8051F390/1/4/5 Block Diagram .......................................................... 18

Figure 1.3. C8051F370/1/4/5 Block Diagram .......................................................... 19

Figure 4.1. C8051F392/3/6/7/8/9 QFN-20 Pinout Diagram (Top View) ................... 25

Figure 4.2. C8051F390/1/4/5 Pinout Diagram (Top View) ...................................... 26

Figure 4.3. C8051F370/1/4/5 Pinout Diagram (Top View) ...................................... 27

Figure 5.1. QFN-20 Package Drawing .................................................................... 28

Figure 5.2. QFN-20 Recommended PCB Land Pattern .......................................... 29

Figure 6.1. QFN-24 Package Drawing .................................................................... 30

Figure 6.2. QFN-24 Recommended PCB Land Pattern .......................................... 31

Figure 7.1. Normal Mode Digital Supply Current vs. Frequency ............................. 44

Figure 7.2. Idle Mode Digital Supply Current vs. Frequency ................................... 44

Figure 9.1. ADC0 Functional Block Diagram ........................................................... 48

Figure 9.2. 10-Bit ADC Track and Conversion Example Timing ............................. 51

Figure 9.3. ADC0 Equivalent Input Circuits ............................................................. 52

Figure 9.4. ADC Window Compare Example: Right-Justified, Single-Ended Data . 58

Figure 9.5. ADC Window Compare Example: Left-Justified, Single-Ended Data .... 58

Figure 9.6. ADC0 Multiplexer Block Diagram .......................................................... 59

Figure 10.1. Temperature Sensor Transfer Function .............................................. 62

Figure 10.2. Temperature Sensor Error with 1-Point Calibration at 0 °C ................ 63

Figure 11.1. IDA0 Functional Block Diagram .......................................................... 64

Figure 11.2. IDA1 Functional Block Diagram .......................................................... 65

Figure 11.3. IDA0 Data Word Mapping ................................................................... 66

Figure 12.1. Voltage Reference Functional Block Diagram ..................................... 71

Figure 14.1. Comparator0 Functional Block Diagram ............................................. 74

Figure 14.2. Comparator Hysteresis Plot ................................................................ 75

Figure 14.3. Comparator Input Multiplexer Block Diagram ...................................... 78

Figure 15.1. CIP-51 Block Diagram ......................................................................... 80

Figure 17.1. C8051F39x/37x Memory Map ............................................................. 91

Figure 17.2. Flash Program Memory Map ............................................................... 92

Figure 19.1. SFR Page Stack ................................................................................ 100

Figure 19.2. SFR Page Stack While Using SFR Page 0x0F To Access TS0CN .. 101

Figure 19.3. SFR Page Stack After SPI0 Interrupt Occurs .................................... 102

Figure 19.4. SFR Page Stack Upon PCA Interrupt Occurring During a SPI0 ISR 103

Figure 19.5. SFR Page Stack Upon Return from PCA0 Interrupt ......................... 104

Figure 19.6. SFR Page Stack Upon Return From SPI0 Interrupt .......................... 105

Figure 21.1. Security Byte Decoding ..................................................................... 131

Figure 22.1. Slave Address Byte Definition ........................................................... 139

Figure 22.2. Write Operation (Single Byte) ............................................................ 140

Figure 22.3. Write Operation (Multiple Bytes) ....................................................... 140

Figure 22.4. Current Address Read Operation (Single Byte) ................................ 141

Figure 22.5. Current Address Read Operation (Multiple Bytes) ............................ 142

Figure 22.6. Selective Address Read (Single Byte) .............................................. 143

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Preliminary Rev. 0.71

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