C8051F370 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F370

50 MIPS 16 kB Flash, 512B EEPROM Mixed-Signal MCU

Silicon Laboratories 

C8051F39x/37x

Figure 22.7. Selective Address Read (Multiple Bytes) .......................................... 144

Figure 23.1. CRC0 Block Diagram ........................................................................ 145

Figure 23.2. Bit Reverse Register ......................................................................... 147

Figure 24.1. Reset Sources ................................................................................... 153

Figure 24.2. Power-On and VDD Monitor Reset Timing ....................................... 154

Figure 26.1. Oscillator Options .............................................................................. 162

Figure 26.2. External Crystal Example .................................................................. 168

Figure 27.1. Port I/O Functional Block Diagram .................................................... 171

Figure 27.2. Port I/O Cell Block Diagram .............................................................. 172

Figure 27.3. Crossbar Priority Decoder - Possible Pin Assignments .................... 176

Figure 27.4. Crossbar Priority Decoder Example .................................................. 177

Figure 28.1. SMBus0 Block Diagram .................................................................... 190

Figure 28.2. Typical SMBus Configuration ............................................................ 191

Figure 28.3. SMBus Transaction ........................................................................... 192

Figure 28.4. Typical SMBus SCL Generation ........................................................ 194

Figure 28.5. Typical Master Write Sequence ........................................................ 209

Figure 28.6. Typical Master Read Sequence ........................................................ 210

Figure 28.7. Typical Slave Write Sequence .......................................................... 211

Figure 28.8. Typical Slave Read Sequence .......................................................... 212

Figure 29.1. UART0 Block Diagram ...................................................................... 218

Figure 29.2. UART0 Baud Rate Logic ................................................................... 219

Figure 29.3. UART Interconnect Diagram ............................................................. 220

Figure 29.4. 8-Bit UART Timing Diagram .............................................................. 220

Figure 29.5. 9-Bit UART Timing Diagram .............................................................. 221

Figure 29.6. UART Multi-Processor Mode Interconnect Diagram ......................... 222

Figure 30.1. SPI Block Diagram ............................................................................ 226

Figure 30.2. Multiple-Master Mode Connection Diagram ...................................... 228

Figure 30.3. 3-Wire Single Master and 3-Wire Single Slave

Mode Connection Diagram .............................................................................. 229

Figure 30.4. 4-Wire Single Master Mode and 4-Wire Slave

Mode Connection Diagram .............................................................................. 229

Figure 30.5. Master Mode Data/Clock Timing ....................................................... 231

Figure 30.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 231

Figure 30.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 232

Figure 30.8. SPI Master Timing (CKPHA = 0) ....................................................... 236

Figure 30.9. SPI Master Timing (CKPHA = 1) ....................................................... 237

Figure 30.10. SPI Slave Timing (CKPHA = 0) ....................................................... 237

Figure 30.11. SPI Slave Timing (CKPHA = 1) ....................................................... 238

Figure 31.1. T0 Mode 0 Block Diagram ................................................................. 244

Figure 31.2. T0 Mode 2 Block Diagram ................................................................. 245

Figure 31.3. T0 Mode 3 Block Diagram ................................................................. 246

Figure 31.4. Timer 2 16-Bit Mode Block Diagram ................................................. 251

Figure 31.5. Timer 2 8-Bit Mode Block Diagram ................................................... 252

Figure 31.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram ... 253

Figure 31.7. Timer 3 16-Bit Mode Block Diagram ................................................. 257

Preliminary Rev. 0.71

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